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[src/trunk]: src/sys/dev/pci No functional change:
details: https://anonhg.NetBSD.org/src/rev/ecfb59998618
branches: trunk
changeset: 797655:ecfb59998618
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Fri Jul 25 01:05:00 2014 +0000
description:
No functional change:
- move NVM related values to the bottom.
- sort in register's address.
diffstat:
sys/dev/pci/if_wmreg.h | 1184 +++++++++++++++++++++++------------------------
1 files changed, 583 insertions(+), 601 deletions(-)
diffs (truncated from 1205 to 300 lines):
diff -r 1c073f37c5a4 -r ecfb59998618 sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h Thu Jul 24 23:30:38 2014 +0000
+++ b/sys/dev/pci/if_wmreg.h Fri Jul 25 01:05:00 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.57 2014/07/11 02:23:44 msaitoh Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.58 2014/07/25 01:05:00 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -291,6 +291,588 @@
#define EECD_SEC1VAL (1U << 22) /* Sector One Valid */
#define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */
+#define WMREG_EERD 0x0014 /* EEPROM read */
+#define EERD_DONE 0x02 /* done bit */
+#define EERD_START 0x01 /* First bit for telling part to start operation */
+#define EERD_ADDR_SHIFT 2 /* Shift to the address bits */
+#define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */
+
+#define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */
+#define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */
+#define CTRL_EXT_SWDPINS_SHIFT 4
+#define CTRL_EXT_SWDPINS_MASK 0x0d
+/* The bit order of the SW Definable pin is not 6543 but 3654! */
+#define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT \
+ + ((x) == 3 ? 3 : ((x) - 4))))
+#define CTRL_EXT_SWDPIO_SHIFT 8
+#define CTRL_EXT_SWDPIO_MASK 0x0d
+#define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \
+ + ((x) == 3 ? 3 : ((x) - 4))))
+#define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */
+#define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */
+#define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */
+#define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */
+#define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */
+#define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */
+#define CTRL_EXT_LINK_MODE_MASK 0x00C00000
+#define CTRL_EXT_LINK_MODE_GMII 0x00000000
+#define CTRL_EXT_LINK_MODE_KMRN 0x00000000
+#define CTRL_EXT_LINK_MODE_1000KX 0x00400000
+#define CTRL_EXT_LINK_MODE_SGMII 0x00800000
+#define CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
+#define CTRL_EXT_LINK_MODE_TBI 0x00C00000
+#define CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
+#define CTRL_EXT_PHYPDEN 0x00100000
+#define CTRL_EXT_I2C_ENA 0x02000000 /* I2C enable */
+#define CTRL_EXT_DRV_LOAD 0x10000000
+
+#define WMREG_MDIC 0x0020 /* MDI Control Register */
+#define MDIC_DATA(x) ((x) & 0xffff)
+#define MDIC_REGADD(x) ((x) << 16)
+#define MDIC_PHY_SHIFT 21
+#define MDIC_PHY_MASK __BITS(25, 21)
+#define MDIC_PHYADD(x) ((x) << 21)
+#define MDIC_OP_WRITE (1U << 26)
+#define MDIC_OP_READ (2U << 26)
+#define MDIC_READY (1U << 28)
+#define MDIC_I (1U << 29) /* interrupt on MDI complete */
+#define MDIC_E (1U << 30) /* MDI error */
+#define MDIC_DEST (1U << 31) /* Destination */
+
+#define WMREG_SCTL 0x0024 /* SerDes Control - RW */
+/*
+ * These 4 macros are also used for other 8bit control registers on the
+ * 82575
+ */
+#define SCTL_CTL_READY (1U << 31)
+#define SCTL_CTL_DATA_MASK 0x000000ff
+#define SCTL_CTL_ADDR_SHIFT 8
+#define SCTL_CTL_POLL_TIMEOUT 640
+
+#define WMREG_FCAL 0x0028 /* Flow Control Address Low */
+#define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */
+
+#define WMREG_FCAH 0x002c /* Flow Control Address High */
+#define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */
+
+#define WMREG_FCT 0x0030 /* Flow Control Type */
+
+#define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */
+#define KUMCTRLSTA_MASK 0x0000FFFF
+#define KUMCTRLSTA_OFFSET 0x001F0000
+#define KUMCTRLSTA_OFFSET_SHIFT 16
+#define KUMCTRLSTA_REN 0x00200000
+
+#define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
+#define KUMCTRLSTA_OFFSET_CTRL 0x00000001
+#define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
+#define KUMCTRLSTA_OFFSET_DIAG 0x00000003
+#define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
+#define KUMCTRLSTA_OFFSET_K1_CONFIG 0x00000007
+#define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
+#define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
+#define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
+#define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
+
+/* FIFO Control */
+#define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
+#define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
+
+/* In-Band Control */
+#define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500
+#define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
+
+/* Diag */
+#define KUMCTRLSTA_DIAG_NELPBK 0x1000
+
+/* K1 Config */
+#define KUMCTRLSTA_K1_ENABLE 0x0002
+
+/* Half-Duplex Control */
+#define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
+#define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
+
+#define WMREG_VET 0x0038 /* VLAN Ethertype */
+#define WMREG_MDPHYA 0x003C /* PHY address - RW */
+#define WMREG_RAL_BASE 0x0040 /* Receive Address List */
+#define WMREG_CORDOVA_RAL_BASE 0x5400
+#define WMREG_RAL_LO(b, x) ((b) + ((x) << 3))
+#define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4)
+ /*
+ * Receive Address List: The LO part is the low-order 32-bits
+ * of the MAC address. The HI part is the high-order 16-bits
+ * along with a few control bits.
+ */
+#define RAL_AS(x) ((x) << 16) /* address select */
+#define RAL_AS_DEST RAL_AS(0) /* (cordova?) */
+#define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */
+#define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */
+#define RAL_AV (1U << 31) /* entry is valid */
+
+#define WM_RAL_TABSIZE 15 /* RAL size for old devices */
+#define WM_RAL_TABSIZE_ICH8 7 /* RAL size for ICH* and PCH* */
+#define WM_RAL_TABSIZE_82575 16 /* RAL size for 82575 */
+#define WM_RAL_TABSIZE_82576 24 /* RAL size for 82576 and 82580 */
+#define WM_RAL_TABSIZE_I350 32 /* RAL size for I350 */
+
+#define WMREG_ICR 0x00c0 /* Interrupt Cause Register */
+#define ICR_TXDW (1U << 0) /* Tx desc written back */
+#define ICR_TXQE (1U << 1) /* Tx queue empty */
+#define ICR_LSC (1U << 2) /* link status change */
+#define ICR_RXSEQ (1U << 3) /* receive sequence error */
+#define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */
+#define ICR_RXO (1U << 6) /* Rx overrun */
+#define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */
+#define ICR_MDAC (1U << 9) /* MDIO access complete */
+#define ICR_RXCFG (1U << 10) /* Receiving /C/ */
+#define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */
+#define ICR_INT (1U << 31) /* device generated an interrupt */
+
+#define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */
+#define ITR_IVAL_MASK 0xffff /* Interval mask */
+#define ITR_IVAL_SHIFT 0 /* Interval shift */
+
+#define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */
+ /* See ICR bits. */
+
+#define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */
+ /* See ICR bits. */
+
+#define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */
+ /* See ICR bits. */
+
+#define WMREG_RCTL 0x0100 /* Receive Control */
+#define RCTL_EN (1U << 1) /* receiver enable */
+#define RCTL_SBP (1U << 2) /* store bad packets */
+#define RCTL_UPE (1U << 3) /* unicast promisc. enable */
+#define RCTL_MPE (1U << 4) /* multicast promisc. enable */
+#define RCTL_LPE (1U << 5) /* large packet enable */
+#define RCTL_LBM(x) ((x) << 6) /* loopback mode */
+#define RCTL_LBM_NONE RCTL_LBM(0)
+#define RCTL_LBM_PHY RCTL_LBM(3)
+#define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */
+#define RCTL_RDMTS_1_2 RCTL_RDMTS(0)
+#define RCTL_RDMTS_1_4 RCTL_RDMTS(1)
+#define RCTL_RDMTS_1_8 RCTL_RDMTS(2)
+#define RCTL_RDMTS_MASK RCTL_RDMTS(3)
+#define RCTL_MO(x) ((x) << 12) /* multicast offset */
+#define RCTL_BAM (1U << 15) /* broadcast accept mode */
+#define RCTL_2k (0 << 16) /* 2k Rx buffers */
+#define RCTL_1k (1 << 16) /* 1k Rx buffers */
+#define RCTL_512 (2 << 16) /* 512 byte Rx buffers */
+#define RCTL_256 (3 << 16) /* 256 byte Rx buffers */
+#define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */
+#define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */
+#define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */
+#define RCTL_DPF (1U << 22) /* discard pause frames */
+#define RCTL_PMCF (1U << 23) /* pass MAC control frames */
+#define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */
+#define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */
+
+#define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */
+#define WMREG_RDTR 0x2820
+#define RDTR_FPD (1U << 31) /* flush partial descriptor */
+
+#define WMREG_LTRC 0x01a0 /* Latency Tolerance Reportiong Control */
+
+#define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */
+#define WMREG_RDBAL 0x2800
+#define WMREG_RDBAL_2 0x0c00 /* for 82576 ... */
+
+#define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */
+#define WMREG_RDBAH 0x2804
+#define WMREG_RDBAH_2 0x0c04 /* for 82576 ... */
+
+#define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */
+#define WMREG_RDLEN 0x2808
+#define WMREG_RDLEN_2 0x0c08 /* for 82576 ... */
+
+#define WMREG_SRRCTL 0x280c /* additional recv control used in 82575 ... */
+#define WMREG_SRRCTL_2 0x0c0c /* for 82576 ... */
+#define SRRCTL_BSIZEPKT_MASK 0x0000007f
+#define SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
+#define SRRCTL_BSIZEHDRSIZE_MASK 0x00000f00
+#define SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
+#define SRRCTL_DESCTYPE_LEGACY 0x00000000
+#define SRRCTL_DESCTYPE_ADV_ONEBUF (1U << 25)
+#define SRRCTL_DESCTYPE_HDR_SPLIT (2U << 25)
+#define SRRCTL_DESCTYPE_HDR_REPLICATION (3U << 25)
+#define SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT (4U << 25)
+#define SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS (5U << 25) /* 82575 only */
+#define SRRCTL_DESCTYPE_MASK (7U << 25)
+#define SRRCTL_DROP_EN 0x80000000
+
+#define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */
+#define WMREG_RDH 0x2810
+#define WMREG_RDH_2 0x0c10 /* for 82576 ... */
+
+#define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */
+#define WMREG_RDT 0x2818
+#define WMREG_RDT_2 0x0c18 /* for 82576 ... */
+
+#define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */
+#define WMREG_RXDCTL_2 0x0c28 /* for 82576 ... */
+#define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */
+#define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */
+#define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */
+#define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */
+/* flags used starting with 82575 ... */
+#define RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
+#define RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */
+
+#define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */
+#define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */
+#define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */
+#define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */
+#define WMREG_OLD_RDH1 0x0148
+#define WMREG_OLD_RDT1 0x0150
+#define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */
+#define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */
+#define FCRTH_DFLT 0x00008000
+
+#define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */
+#define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */
+#define FCRTL_DFLT 0x00004000
+#define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
+
+#define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */
+#define FCTTV_DFLT 0x00000600
+
+#define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */
+ /* See MII ANAR_X bits. */
+#define TXCW_SYM_PAUSE (1U << 7) /* sym pause request */
+#define TXCW_ASYM_PAUSE (1U << 8) /* asym pause request */
+#define TXCW_TxConfig (1U << 30) /* Tx Config */
+#define TXCW_ANE (1U << 31) /* Autonegotiate */
+
+#define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */
+ /* See MII ANLPAR_X bits. */
+#define RXCW_NC (1U << 26) /* no carrier */
+#define RXCW_IV (1U << 27) /* config invalid */
+#define RXCW_CC (1U << 28) /* config change */
+#define RXCW_C (1U << 29) /* /C/ reception */
+#define RXCW_SYNCH (1U << 30) /* synchronized */
+#define RXCW_ANC (1U << 31) /* autonegotiation complete */
+
+#define WMREG_MTA 0x0200 /* Multicast Table Array */
+#define WMREG_CORDOVA_MTA 0x5200
+
+#define WMREG_TCTL 0x0400 /* Transmit Control Register */
+#define TCTL_EN (1U << 1) /* transmitter enable */
+#define TCTL_PSP (1U << 3) /* pad short packets */
+#define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */
+#define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */
+#define TCTL_SWXOFF (1U << 22) /* software XOFF */
+#define TCTL_RTLC (1U << 24) /* retransmit on late collision */
+#define TCTL_NRTU (1U << 25) /* no retransmit on underrun */
+#define TCTL_MULR (1U << 28) /* multiple request */
+
+#define TX_COLLISION_THRESHOLD 15
+#define TX_COLLISION_DISTANCE_HDX 512
+#define TX_COLLISION_DISTANCE_FDX 64
+
+#define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */
+#define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
+#define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
+
+#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
+
+#define WMREG_TQSA_LO 0x0408
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