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[src/trunk]: src/sys/arch Add initial support for Allwinner A13 and R8 SoCs.
details: https://anonhg.NetBSD.org/src/rev/6a2e1011dc5b
branches: trunk
changeset: 826267:6a2e1011dc5b
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Aug 25 00:07:02 2017 +0000
description:
Add initial support for Allwinner A13 and R8 SoCs.
diffstat:
sys/arch/arm/fdt/fdt_intr.h | 3 +-
sys/arch/arm/sunxi/files.sunxi | 24 ++-
sys/arch/arm/sunxi/sun5i_a13_ccu.c | 263 ++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sun5i_a13_ccu.h | 145 ++++++++++++++++++
sys/arch/arm/sunxi/sun5i_a13_gpio.c | 128 ++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu.h | 9 +-
sys/arch/arm/sunxi/sunxi_ccu_div.c | 10 +-
sys/arch/arm/sunxi/sunxi_ccu_prediv.c | 9 +-
sys/arch/arm/sunxi/sunxi_gpio.c | 7 +-
sys/arch/arm/sunxi/sunxi_gpio.h | 6 +-
sys/arch/arm/sunxi/sunxi_intc.c | 272 ++++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_mmc.c | 5 +-
sys/arch/arm/sunxi/sunxi_platform.c | 86 +++++++++-
sys/arch/arm/sunxi/sunxi_timer.c | 200 +++++++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_twi.c | 5 +-
sys/arch/arm/sunxi/sunxi_usbphy.c | 6 +-
sys/arch/evbarm/conf/SUNXI | 23 ++-
sys/arch/evbarm/conf/std.sunxi | 3 +-
18 files changed, 1169 insertions(+), 35 deletions(-)
diffs (truncated from 1555 to 300 lines):
diff -r 0bc42ce646e6 -r 6a2e1011dc5b sys/arch/arm/fdt/fdt_intr.h
--- a/sys/arch/arm/fdt/fdt_intr.h Thu Aug 24 23:45:08 2017 +0000
+++ b/sys/arch/arm/fdt/fdt_intr.h Fri Aug 25 00:07:02 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fdt_intr.h,v 1.1 2017/05/30 22:00:25 jmcneill Exp $ */
+/* $NetBSD: fdt_intr.h,v 1.2 2017/08/25 00:07:02 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -34,6 +34,7 @@
#ifndef _LOCORE
#define __HAVE_PIC_SET_PRIORITY
+#define __HAVE_PIC_PENDING_INTRS
#define PIC_MAXSOURCES 256
#define PIC_MAXMAXSOURCES (PIC_MAXSOURCES + 32)
diff -r 0bc42ce646e6 -r 6a2e1011dc5b sys/arch/arm/sunxi/files.sunxi
--- a/sys/arch/arm/sunxi/files.sunxi Thu Aug 24 23:45:08 2017 +0000
+++ b/sys/arch/arm/sunxi/files.sunxi Fri Aug 25 00:07:02 2017 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.16 2017/08/06 17:15:45 jmcneill Exp $
+# $NetBSD: files.sunxi,v 1.17 2017/08/25 00:07:03 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -27,6 +27,11 @@
file arch/arm/sunxi/sunxi_ccu_phase.c sunxi_ccu
file arch/arm/sunxi/sunxi_ccu_prediv.c sunxi_ccu
+# CCU (A13)
+device sun5ia13ccu: sunxi_ccu
+attach sun5ia13ccu at fdt with sunxi_a13_ccu
+file arch/arm/sunxi/sun5i_a13_ccu.c sunxi_a13_ccu
+
# CCU (A31)
device sun6ia31ccu: sunxi_ccu
attach sun6ia31ccu at fdt with sunxi_a31_ccu
@@ -52,10 +57,16 @@
attach sunxigates at fdt with sunxi_gates
file arch/arm/sunxi/sunxi_gates.c sunxi_gates
+# Interrupt controller
+device sunxiintc: pic, pic_splfuncs
+attach sunxiintc at fdt with sunxi_intc
+file arch/arm/sunxi/sunxi_intc.c sunxi_intc
+
# GPIO
device sunxigpio: gpiobus
attach sunxigpio at fdt with sunxi_gpio
file arch/arm/sunxi/sunxi_gpio.c sunxi_gpio
+file arch/arm/sunxi/sun5i_a13_gpio.c sunxi_gpio & soc_sun5i_a13
file arch/arm/sunxi/sun6i_a31_gpio.c sunxi_gpio & soc_sun6i_a31
file arch/arm/sunxi/sun8i_a83t_gpio.c sunxi_gpio & soc_sun8i_a83t
file arch/arm/sunxi/sun8i_h3_gpio.c sunxi_gpio & soc_sun8i_h3
@@ -103,6 +114,11 @@
attach sunxiemac at fdt with sunxi_emac
file arch/arm/sunxi/sunxi_emac.c sunxi_emac
+# Timer
+device sunxitimer
+attach sunxitimer at fdt with sunxi_timer
+file arch/arm/sunxi/sunxi_timer.c sunxi_timer
+
# Watchdog
device sunxiwdt: sysmon_wdog
attach sunxiwdt at fdt with sunxi_wdt
@@ -125,10 +141,12 @@
# SOC parameters
defflag opt_soc.h SOC_SUNXI
+defflag opt_soc.h SOC_SUN5I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN5I_A13: SOC_SUN5I
+defflag opt_soc.h SOC_SUN6I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN6I_A31: SOC_SUN6I
defflag opt_soc.h SOC_SUN8I: SOC_SUNXI
defflag opt_soc.h SOC_SUN8I_A83T: SOC_SUN8I
defflag opt_soc.h SOC_SUN8I_H3: SOC_SUN8I
-defflag opt_soc.h SOC_SUN6I: SOC_SUNXI
-defflag opt_soc.h SOC_SUN6I_A31: SOC_SUN6I
defflag opt_soc.h SOC_SUN50I: SOC_SUNXI
defflag opt_soc.h SOC_SUN50I_A64: SOC_SUN50I
diff -r 0bc42ce646e6 -r 6a2e1011dc5b sys/arch/arm/sunxi/sun5i_a13_ccu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/sun5i_a13_ccu.c Fri Aug 25 00:07:02 2017 +0000
@@ -0,0 +1,263 @@
+/* $NetBSD: sun5i_a13_ccu.c,v 1.1 2017/08/25 00:07:03 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun5i_a13_ccu.c,v 1.1 2017/08/25 00:07:03 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun5i_a13_ccu.h>
+
+#define PLL1_CFG_REG 0x000
+#define PLL6_CFG_REG 0x028
+#define OSC24M_CFG_REG 0x050
+#define CPU_AHB_APB0_CFG_REG 0x054
+#define APB1_CLK_DIV_REG 0x058
+#define AHB_GATING_REG0 0x060
+#define AHB_GATING_REG1 0x064
+#define APB0_GATING_REG 0x068
+#define APB1_GATING_REG 0x06c
+#define USBPHY_CFG_REG 0x0cc
+#define BE_CFG_REG 0x104
+#define FE_CFG_REG 0x10c
+#define CSI_CFG_REG 0x134
+#define VE_CFG_REG 0x13c
+#define MALI_CLOCK_CFG_REG 0x154
+#define IEP_SCLK_CFG_REG 0x160
+
+static int sun5i_a13_ccu_match(device_t, cfdata_t, void *);
+static void sun5i_a13_ccu_attach(device_t, device_t, void *);
+
+static const char * const compatible[] = {
+ "allwinner,sun5i-a13-ccu",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_a13_ccu, sizeof(struct sunxi_ccu_softc),
+ sun5i_a13_ccu_match, sun5i_a13_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun5i_a13_ccu_resets[] = {
+ SUNXI_CCU_RESET(A13_RST_USB_PHY0, USBPHY_CFG_REG, 0),
+ SUNXI_CCU_RESET(A13_RST_USB_PHY1, USBPHY_CFG_REG, 1),
+
+ /* Missing: GPS */
+
+ SUNXI_CCU_RESET(A13_RST_DE_BE, BE_CFG_REG, 30),
+
+ SUNXI_CCU_RESET(A13_RST_DE_FE, FE_CFG_REG, 30),
+
+ /* Missing: TVE */
+
+ /* Missing: LCD */
+
+ SUNXI_CCU_RESET(A13_RST_CSI, CSI_CFG_REG, 30),
+
+ SUNXI_CCU_RESET(A13_RST_VE, VE_CFG_REG, 0),
+
+ SUNXI_CCU_RESET(A13_RST_GPU, MALI_CLOCK_CFG_REG, 30),
+
+ SUNXI_CCU_RESET(A13_RST_IEP, IEP_SCLK_CFG_REG, 30),
+};
+
+static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" };
+static const char *axi_parents[] = { "cpu" };
+static const char *ahb_parents[] = { "axi", "cpu", "pll_periph", NULL };
+static const char *apb0_parents[] = { "ahb" };
+static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc", NULL };
+
+static struct sunxi_ccu_clk sun5i_a13_ccu_clks[] = {
+ SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc",
+ OSC24M_CFG_REG, 0),
+
+ SUNXI_CCU_NKMP(A13_CLK_PLL_CORE, "pll_core", "osc24m",
+ PLL1_CFG_REG, /* reg */
+ __BITS(12,8), /* n */
+ __BITS(5,4), /* k */
+ __BITS(1,0), /* m */
+ __BITS(17,16), /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT),
+
+ SUNXI_CCU_NKMP(A13_CLK_PERIPH, "pll_periph", "osc24m",
+ PLL6_CFG_REG, /* reg */
+ __BITS(12,8), /* n */
+ __BITS(5,4), /* k */
+ __BITS(1,0), /* m */
+ 0, /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_DIVIDE_BY_TWO | SUNXI_CCU_NKMP_FACTOR_N_EXACT),
+
+ SUNXI_CCU_PREDIV_FIXED(A13_CLK_CPU, "cpu", cpu_parents,
+ CPU_AHB_APB0_CFG_REG, /* reg */
+ 0, /* prediv */
+ __BIT(3), /* prediv_sel */
+ 6, /* prediv_fixed */
+ 0, /* div */
+ __BITS(17,16), /* sel */
+ 0),
+
+ SUNXI_CCU_DIV(A13_CLK_AXI, "axi", axi_parents,
+ CPU_AHB_APB0_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ 0, /* sel */
+ 0),
+
+ SUNXI_CCU_DIV(A13_CLK_AHB, "ahb", ahb_parents,
+ CPU_AHB_APB0_CFG_REG, /* reg */
+ 0, /* div */
+ __BITS(5,4), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_DIV(A13_CLK_APB0, "apb0", apb0_parents,
+ CPU_AHB_APB0_CFG_REG, /* reg */
+ __BITS(9,8), /* div */
+ 0, /* sel */
+ SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(A13_CLK_APB1, "apb1", apb1_parents,
+ APB1_CLK_DIV_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(4,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+
+ /* AHB_GATING_REG0. Missing: SS, EMAC, TS, GPS */
+ SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb",
+ AHB_GATING_REG0, 0),
+ SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb",
+ AHB_GATING_REG0, 1),
+ SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb",
+ AHB_GATING_REG0, 2),
+ SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb",
+ AHB_GATING_REG0, 6),
+ SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb",
+ AHB_GATING_REG0, 7),
+ SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb",
+ AHB_GATING_REG0, 8),
+ SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb",
+ AHB_GATING_REG0, 9),
+ SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb",
+ AHB_GATING_REG0, 10),
+ SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb",
+ AHB_GATING_REG0, 13),
+ SUNXI_CCU_GATE(A13_CLK_AHB_SDRAM, "ahb-sdram", "ahb",
+ AHB_GATING_REG0, 14),
+ SUNXI_CCU_GATE(A13_CLK_AHB_SPI0, "ahb-spi0", "ahb",
+ AHB_GATING_REG0, 20),
+ SUNXI_CCU_GATE(A13_CLK_AHB_SPI1, "ahb-spi1", "ahb",
+ AHB_GATING_REG0, 21),
+ SUNXI_CCU_GATE(A13_CLK_AHB_SPI2, "ahb-spi2", "ahb",
+ AHB_GATING_REG0, 22),
+ SUNXI_CCU_GATE(A13_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb",
+ AHB_GATING_REG0, 28),
+
+ /* AHB_GATING_REG1. Missing: TVE, HDMI */
+ SUNXI_CCU_GATE(A13_CLK_AHB_VE, "ahb-ve", "ahb",
+ AHB_GATING_REG1, 0),
+ SUNXI_CCU_GATE(A13_CLK_AHB_LCD, "ahb-lcd", "ahb",
+ AHB_GATING_REG1, 4),
+ SUNXI_CCU_GATE(A13_CLK_AHB_CSI, "ahb-csi", "ahb",
+ AHB_GATING_REG1, 8),
+ SUNXI_CCU_GATE(A13_CLK_AHB_DE_BE, "ahb-de_be", "ahb",
+ AHB_GATING_REG1, 12),
+ SUNXI_CCU_GATE(A13_CLK_AHB_DE_FE, "ahb-de_fe", "ahb",
+ AHB_GATING_REG1, 14),
+ SUNXI_CCU_GATE(A13_CLK_AHB_IEP, "ahb-iep", "ahb",
+ AHB_GATING_REG1, 19),
+ SUNXI_CCU_GATE(A13_CLK_AHB_GPU, "ahb-gpu", "ahb",
+ AHB_GATING_REG1, 20),
+
+ /* APB0_GATING_REG. Missing: SPDIF, I2S, KEYPAD */
+ SUNXI_CCU_GATE(A13_CLK_APB0_CODEC, "apb0-codec", "apb0",
+ APB0_GATING_REG, 0),
+ SUNXI_CCU_GATE(A13_CLK_APB0_PIO, "apb0-pio", "apb0",
+ APB0_GATING_REG, 5),
+ SUNXI_CCU_GATE(A13_CLK_APB0_IR, "apb0-ir", "apb0",
+ APB0_GATING_REG, 6),
+
+ /* APB1_GATING_REG. Missing: UART0, UART2 */
+ SUNXI_CCU_GATE(A13_CLK_APB1_I2C0, "apb1-i2c0", "apb1",
+ APB1_GATING_REG, 0),
+ SUNXI_CCU_GATE(A13_CLK_APB1_I2C1, "apb1-i2c1", "apb1",
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