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[src/trunk]: src/sys/arch/arm/cortex If we're going to allow pl0 to access vi...



details:   https://anonhg.NetBSD.org/src/rev/3f5b4050716b
branches:  trunk
changeset: 836172:3f5b4050716b
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sun Sep 30 10:34:38 2018 +0000

description:
If we're going to allow pl0 to access virtual and physical counters then
we should allow it from all CPUs.

kern/53630 (openssl fallout on arm)

diffstat:

 sys/arch/arm/cortex/gtmr.c |  17 +++++++++--------
 1 files changed, 9 insertions(+), 8 deletions(-)

diffs (45 lines):

diff -r 4c6d164b38e8 -r 3f5b4050716b sys/arch/arm/cortex/gtmr.c
--- a/sys/arch/arm/cortex/gtmr.c        Sun Sep 30 10:08:13 2018 +0000
+++ b/sys/arch/arm/cortex/gtmr.c        Sun Sep 30 10:34:38 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: gtmr.c,v 1.35 2018/09/16 13:21:36 jmcneill Exp $       */
+/*     $NetBSD: gtmr.c,v 1.36 2018/09/30 10:34:38 skrll Exp $  */
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.35 2018/09/16 13:21:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.36 2018/09/30 10:34:38 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -120,12 +120,6 @@
                aprint_debug_dev(self, "enabling Allwinner A64 timer workaround\n");
        }
 
-       /*
-        * Enable the virtual counter to be accessed from usermode.
-        */
-       gtmr_cntk_ctl_write(gtmr_cntk_ctl_read() |
-           CNTKCTL_PL0VCTEN | CNTKCTL_PL0PCTEN);
-
        self->dv_private = sc;
        sc->sc_dev = self;
 
@@ -195,6 +189,13 @@
        int s = splsched();
 
        /*
+        * Allow the virtual and physical counters to be accessed from
+        * usermode. (PL0)
+        */
+       gtmr_cntk_ctl_write(gtmr_cntk_ctl_read() |
+           CNTKCTL_PL0VCTEN | CNTKCTL_PL0PCTEN);
+
+       /*
         * enable timer and stop masking the timer.
         */
        gtmr_cntv_ctl_write(CNTCTL_ENABLE);



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