[src/trunk]: src/sys/arch/x86/include Add 3way and 6way of L2 cache or TLB on...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/06068596165f
branches:  trunk
changeset: 831106:06068596165f
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Mar 12 06:20:33 2018 +0000

description:
Add 3way and 6way of L2 cache or TLB on AMD CPU.

diffstat:

 sys/arch/x86/include/cacheinfo.h |  4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diffs (19 lines):

diff -r 7b968c9f4053 -r 06068596165f sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h  Mon Mar 12 01:15:00 2018 +0000
+++ b/sys/arch/x86/include/cacheinfo.h  Mon Mar 12 06:20:33 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cacheinfo.h,v 1.24 2018/03/09 08:49:32 msaitoh Exp $   */
+/*     $NetBSD: cacheinfo.h,v 1.25 2018/03/12 06:20:33 msaitoh Exp $   */
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -342,7 +342,9 @@
 #define AMD_L2CACHE_INFO { \
 __CI_TBL(0, 0x01,    1, 0, 0, NULL), \
 __CI_TBL(0, 0x02,    2, 0, 0, NULL), \
+__CI_TBL(0, 0x03,    3, 0, 0, NULL), \
 __CI_TBL(0, 0x04,    4, 0, 0, NULL), \
+__CI_TBL(0, 0x05,    6, 0, 0, NULL), \
 __CI_TBL(0, 0x06,    8, 0, 0, NULL), \
 __CI_TBL(0, 0x08,   16, 0, 0, NULL), \
 __CI_TBL(0, 0x0a,   32, 0, 0, NULL), \