[src/trunk]: src/sys/external/bsd/drm2/i915drm Flush chipset writes after GGT...

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c7bb6e954a23
branches:  trunk
changeset: 834286:c7bb6e954a23
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Mon Aug 06 00:30:15 2018 +0000

description:
Flush chipset writes after GGTT update.

Echoes Linux commit:

commit 8516673a996870ea0ceb337ee4f83c33c5ec3111
Author: Chris Wilson <chris%chris-wilson.co.uk@localhost>
Date:   Fri Dec 8 21:46:16 2017 +0000

    agp/intel: Flush all chipset writes after updating the GGTT

    Before accessing the GGTT we must flush the PTE writes and make them
    visible to the chipset, or else the indirect access may end up in the
    wrong page. In commit 3497971a71d8 ("agp/intel: Flush chipset writes
    after updating a single PTE"), we noticed corruption of the uploads for
    pwrite and for capturing GPU error states, but it was presumed that the
    explicit calls to intel_gtt_chipset_flush() were sufficient for the
    execbuffer path. However, we have not been flushing the chipset between
    the PTE writes and access via the GTT itself.

    For simplicity, do the flush after any PTE update rather than try and
    batch the flushes on a just-in-time basis.

    References: 3497971a71d8 ("agp/intel: Flush chipset writes after updating a single PTE")
    Signed-off-by: Chris Wilson <chris%chris-wilson.co.uk@localhost>
    Cc: Tvrtko Ursulin <tvrtko.ursulin%intel.com@localhost>
    Cc: Mika Kuoppala <mika.kuoppala%intel.com@localhost>
    Cc: drm-intel-fixes%lists.freedesktop.org@localhost
    Reviewed-by: Joonas Lahtinen <joonas.lahtinen%linux.intel.com@localhost>
    Link: https://patchwork.freedesktop.org/patch/msgid/20171208214616.30147-1-chris%chris-wilson.co.uk@localhost

XXX pullup

diffstat:

 sys/external/bsd/drm2/i915drm/intel_gtt.c |  5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diffs (26 lines):

diff -r 4948f57468b3 -r c7bb6e954a23 sys/external/bsd/drm2/i915drm/intel_gtt.c
--- a/sys/external/bsd/drm2/i915drm/intel_gtt.c Mon Aug 06 00:30:07 2018 +0000
+++ b/sys/external/bsd/drm2/i915drm/intel_gtt.c Mon Aug 06 00:30:15 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: intel_gtt.c,v 1.5 2015/03/06 22:03:06 riastradh Exp $  */
+/*     $NetBSD: intel_gtt.c,v 1.6 2018/08/06 00:30:15 riastradh Exp $  */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 /* Intel GTT stubs */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_gtt.c,v 1.5 2015/03/06 22:03:06 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_gtt.c,v 1.6 2018/08/06 00:30:15 riastradh Exp $");
 
 #include <sys/types.h>
 #include <sys/bus.h>
@@ -176,6 +176,7 @@
                va += PAGE_SIZE;
        }
        agp_i810_post_gtt_entry(isc, (va - PAGE_SIZE));
+       intel_gtt_chipset_flush();
 }
 
 void