Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys add Analogix DisplayPort core driver
details: https://anonhg.NetBSD.org/src/rev/60a79e1dfec7
branches: trunk
changeset: 847338:60a79e1dfec7
user: jakllsch <jakllsch%NetBSD.org@localhost>
date: Thu Dec 19 00:23:57 2019 +0000
description:
add Analogix DisplayPort core driver
diffstat:
sys/conf/files | 6 +-
sys/dev/ic/anx_dp.c | 1064 +++++++++++++++++++++++++++++++++++++++++++++++++++
sys/dev/ic/anx_dp.h | 77 +++
3 files changed, 1146 insertions(+), 1 deletions(-)
diffs (truncated from 1169 to 300 lines):
diff -r 18846233b3eb -r 60a79e1dfec7 sys/conf/files
--- a/sys/conf/files Wed Dec 18 21:46:03 2019 +0000
+++ b/sys/conf/files Thu Dec 19 00:23:57 2019 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files,v 1.1246 2019/12/18 07:37:18 maxv Exp $
+# $NetBSD: files,v 1.1247 2019/12/19 00:23:57 jakllsch Exp $
# @(#)files.newconf 7.5 (Berkeley) 5/10/93
version 20171118
@@ -1489,6 +1489,10 @@
file dev/ic/dw_hdmi.c dwhdmi
file dev/ic/dw_hdmi_phy.c dwhdmi
+# Analogix DisplayPort
+device anxdp: edid, videomode, drmkms, drmkms_i2c
+file dev/ic/anx_dp.c anxdp
+
#
# File systems
#
diff -r 18846233b3eb -r 60a79e1dfec7 sys/dev/ic/anx_dp.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/ic/anx_dp.c Thu Dec 19 00:23:57 2019 +0000
@@ -0,0 +1,1064 @@
+/* $NetBSD: anx_dp.c,v 1.1 2019/12/19 00:23:57 jakllsch Exp $ */
+
+/*-
+ * Copyright (c) 2019 Jonathan A. Kollasch <jakllsch%kollasch.net@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: anx_dp.c,v 1.1 2019/12/19 00:23:57 jakllsch Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/conf.h>
+
+#include <dev/ic/anx_dp.h>
+
+#if ANXDP_AUDIO
+#include <dev/audio/audio_dai.h>
+#endif
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_edid.h>
+
+#define ANXDP_DP_TX_VERSION 0x010
+#define ANXDP_TX_SW_RESET 0x014
+#define RESET_DP_TX __BIT(0)
+#define ANXDP_FUNC_EN_1 0x018
+#define MASTER_VID_FUNC_EN_N __BIT(7)
+#define RK_VID_CAP_FUNC_EN_N __BIT(6)
+#define SLAVE_VID_FUNC_EN_N __BIT(5)
+#define RK_VID_FIFO_FUNC_EN_N __BIT(5)
+#define AUD_FIFO_FUNC_EN_N __BIT(4)
+#define AUD_FUNC_EN_N __BIT(3)
+#define HDCP_FUNC_EN_N __BIT(2)
+#define CRC_FUNC_EN_N __BIT(1)
+#define SW_FUNC_EN_N __BIT(0)
+#define ANXDP_FUNC_EN_2 0x01c
+#define SSC_FUNC_EN_N __BIT(7)
+#define AUX_FUNC_EN_N __BIT(2)
+#define SERDES_FIFO_FUNC_EN_N __BIT(1)
+#define LS_CLK_DOMAIN_FUNC_EN_N __BIT(0)
+#define ANXDP_VIDEO_CTL_1 0x020
+#define VIDEO_EN __BIT(7)
+#define VIDEO_MUTE __BIT(6)
+#define ANXDP_VIDEO_CTL_2 0x024
+#define ANXDP_VIDEO_CTL_3 0x028
+#define ANXDP_VIDEO_CTL_4 0x02c
+#define ANXDP_VIDEO_CTL_8 0x03c
+#define ANXDP_VIDEO_CTL_10 0x044
+#define F_SEL __BIT(4)
+#define SLAVE_I_SCAN_CFG __BIT(2)
+#define SLAVE_VSYNC_P_CFG __BIT(1)
+#define SLAVE_HSYNC_P_CFG __BIT(0)
+#define ANXDP_PLL_REG_1 0x0fc
+#define REF_CLK_24M __BIT(0)
+#define RKANXDP_PD 0x12c
+#define DP_INC_BG __BIT(7)
+#define DP_EXP_PD __BIT(6)
+#define DP_PHY_PD __BIT(5)
+#define RK_AUX_PD __BIT(5)
+#define AUX_PD __BIT(4)
+#define RK_PLL_PD __BIT(4)
+#define CHx_PD(x) __BIT(x) /* 0<=x<=3 */
+#define DP_ALL_PD __BITS(7,0)
+#define ANXDP_LANE_MAP 0x35c
+#define ANXDP_ANALOG_CTL_1 0x370
+#define TX_TERMINAL_CTRL_50_OHM __BIT(4)
+#define ANXDP_ANALOG_CTL_2 0x374
+#define SEL_24M __BIT(3)
+#define TX_DVDD_BIT_1_0625V 0x4
+#define ANXDP_ANALOG_CTL_3 0x378
+#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
+#define VCO_BIT_600_MICRO (0x5 << 0)
+#define ANXDP_PLL_FILTER_CTL_1 0x37c
+#define PD_RING_OSC __BIT(6)
+#define AUX_TERMINAL_CTRL_50_OHM (2 << 4)
+#define TX_CUR1_2X __BIT(2)
+#define TX_CUR_16_MA 3
+#define ANXDP_TX_AMP_TUNING_CTL 0x380
+#define ANXDP_AUX_HW_RETRY_CTL 0x390
+#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) __SHIFTIN((x), __BITS(10,8))
+#define AUX_HW_RETRY_INTERVAL_600_US __SHIFTIN(0, __BITS(4,3))
+#define AUX_HW_RETRY_INTERVAL_800_US __SHIFTIN(1, __BITS(4,3))
+#define AUX_HW_RETRY_INTERVAL_1000_US __SHIFTIN(2, __BITS(4,3))
+#define AUX_HW_RETRY_INTERVAL_1800_US __SHIFTIN(3, __BITS(4,3))
+#define AUX_HW_RETRY_COUNT_SEL(x) __SHIFTIN((x), __BITS(2,0))
+#define ANXDP_COMMON_INT_STA_1 0x3c4
+#define PLL_LOCK_CHG __BIT(6)
+#define ANXDP_COMMON_INT_STA_2 0x3c8
+#define ANXDP_COMMON_INT_STA_3 0x3cc
+#define ANXDP_COMMON_INT_STA_4 0x3d0
+#define ANXDP_DP_INT_STA 0x3dc
+#define INT_HPD __BIT(6)
+#define HW_TRAINING_FINISH __BIT(5)
+#define RPLY_RECEIV __BIT(1)
+#define AUX_ERR __BIT(0)
+#define ANXDP_SYS_CTL_1 0x600
+#define DET_STA __BIT(2)
+#define FORCE_DET __BIT(1)
+#define DET_CTRL __BIT(0)
+#define ANXDP_SYS_CTL_2 0x604
+#define ANXDP_SYS_CTL_3 0x608
+#define HPD_STATUS __BIT(6)
+#define F_HPD __BIT(5)
+#define HPD_CTRL __BIT(4)
+#define HDCP_RDY __BIT(3)
+#define STRM_VALID __BIT(2)
+#define F_VALID __BIT(1)
+#define VALID_CTRL __BIT(0)
+#define ANXDP_SYS_CTL_4 0x60c
+#define ANXDP_PKT_SEND_CTL 0x640
+#define ANXDP_HDCP_CTL 0x648
+#define ANXDP_LINK_BW_SET 0x680
+#define ANXDP_LANE_COUNT_SET 0x684
+#define ANXDP_TRAINING_PTN_SET 0x688
+#define SCRAMBLING_DISABLE __BIT(5)
+#define SW_TRAINING_PATTERN_SET_PTN2 __SHIFTIN(2, __BITS(1,0))
+#define SW_TRAINING_PATTERN_SET_PTN1 __SHIFTIN(1, __BITS(1,0))
+#define ANXDP_LNx_LINK_TRAINING_CTL(x) (0x68c + 4 * (x)) /* 0 <= x <= 3 */
+#define MAX_PRE_REACH __BIT(5)
+#define PRE_EMPHASIS_SET(x) __SHIFTIN((x), __BITS(4,3))
+#define MAX_DRIVE_REACH __BIT(2)
+#define DRIVE_CURRENT_SET(x) __SHIFTIN((x), __BITS(1,0))
+#define ANXDP_DEBUG_CTL 0x6c0
+#define PLL_LOCK __BIT(4)
+#define F_PLL_LOCK __BIT(3)
+#define PLL_LOCK_CTRL __BIT(2)
+#define PN_INV __BIT(0)
+#define ANXDP_LINK_DEBUG_CTL 0x6e0
+#define ANXDP_PLL_CTL 0x71c
+#define ANXDP_PHY_PD 0x720
+#define ANXDP_PHY_TEST 0x724
+#define MACRO_RST __BIT(5)
+#define ANXDP_M_AUD_GEN_FILTER_TH 0x778
+#define ANXDP_AUX_CH_STA 0x780
+#define AUX_BUSY __BIT(4)
+#define AUX_STATUS(x) __SHIFTOUT((x), __BITS(3,0))
+#define ANXDP_AUX_ERR_NUM 0x784
+#define ANXDP_AUX_CH_DEFER_CTL 0x788
+#define DEFER_CTRL_EN __BIT(7)
+#define DEFER_COUNT(x) __SHIFTIN((x), __BITS(6,0))
+#define ANXDP_AUX_RX_COMM 0x78c
+#define AUX_RX_COMM_I2C_DEFER __BIT(3)
+#define AUX_RX_COMM_AUX_DEFER __BIT(1)
+#define ANXDP_BUFFER_DATA_CTL 0x790
+#define BUF_CLR __BIT(7)
+#define BUF_DATA_COUNT(x) __SHIFTIN((x), __BITS(4,0))
+#define ANXDP_AUX_CH_CTL_1 0x794
+#define AUX_LENGTH(x) __SHIFTIN((x) - 1, __BITS(7,4))
+#define AUX_TX_COMM(x) __SHIFTOUT(x, __BITS(3,0))
+#define AUX_TX_COMM_DP __BIT(3)
+#define AUX_TX_COMM_MOT __BIT(2)
+#define AUX_TX_COMM_READ __BIT(0)
+#define ANXDP_AUX_ADDR_7_0 0x798
+#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
+#define ANXDP_AUX_ADDR_15_8 0x79c
+#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
+#define ANXDP_AUX_ADDR_19_16 0x7a0
+#define AUX_ADDR_19_16(x) (((x) >> 16) & 0xf)
+#define ANXDP_AUX_CH_CTL_2 0x7a4
+#define ADDR_ONLY __BIT(1)
+#define AUX_EN __BIT(0)
+#define ANXDP_BUF_DATA(x) (0x7c0 + 4 * (x))
+#define ANXDP_SOC_GENERAL_CTL 0x800
+#define AUDIO_MODE_SPDIF_MODE __BIT(8)
+#define VIDEO_MODE_SLAVE_MODE __BIT(1)
+#define ANXDP_CRC_CON 0x890
+#define ANXDP_PLL_REG_2 0x9e4
+#define ANXDP_PLL_REG_3 0x9e8
+#define ANXDP_PLL_REG_4 0x9ec
+#define ANXDP_PLL_REG_5 0xa00
+
+#if ANXDP_AUDIO
+enum anxdp_dai_mixer_ctrl {
+ ANXDP_DAI_OUTPUT_CLASS,
+ ANXDP_DAI_INPUT_CLASS,
+
+ ANXDP_DAI_OUTPUT_MASTER_VOLUME,
+ ANXDP_DAI_INPUT_DAC_VOLUME,
+
+ ANXDP_DAI_MIXER_CTRL_LAST
+};
+
+static void
+anxdp_audio_init(struct anxdp_softc *sc)
+{
+}
+#endif
+
+static inline const bool
+isrockchip(struct anxdp_softc * const sc)
+{
+ return (sc->sc_flags & ANXDP_FLAG_ROCKCHIP) != 0;
+}
+
+static enum drm_connector_status
+anxdp_connector_detect(struct drm_connector *connector, bool force)
+{
+#if 0
+ struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector);
+ struct anxdp_softc * const sc = anxdp_connector->sc;
+
+ /* XXX HPD */
+#endif
+ return connector_status_connected;
+}
+
+static void
+anxdp_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_unregister(connector);
+ drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs anxdp_connector_funcs = {
+ .dpms = drm_helper_connector_dpms,
+ .detect = anxdp_connector_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = anxdp_connector_destroy,
+};
+
+static void
+anxdp_analog_power_up_all(struct anxdp_softc * const sc)
+{
+ const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD;
+
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, pd_reg, DP_ALL_PD);
+ delay(15);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, pd_reg,
+ DP_ALL_PD & ~DP_INC_BG);
+ delay(15);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, pd_reg, 0);
+}
+
+static int
+anxdp_await_pll_lock(struct anxdp_softc * const sc)
+{
+ u_int timeout;
+
+ for (timeout = 0; timeout < 100; timeout++) {
+ if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_DEBUG_CTL) &
+ PLL_LOCK) != 0)
+ return 0;
+ delay(20);
+ }
+
+ return ETIMEDOUT;
+}
Home |
Main Index |
Thread Index |
Old Index