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[src/trunk]: src/sys/arch Add support for NVIDIA Tegra X1.
details: https://anonhg.NetBSD.org/src/rev/5af6f2c8ec8e
branches: trunk
changeset: 825546:5af6f2c8ec8e
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Jul 21 01:01:22 2017 +0000
description:
Add support for NVIDIA Tegra X1.
diffstat:
sys/arch/arm/nvidia/files.tegra | 9 +-
sys/arch/arm/nvidia/tegra124_car.c | 6 +-
sys/arch/arm/nvidia/tegra124_carreg.h | 4 +-
sys/arch/arm/nvidia/tegra210_car.c | 1370 +++++++++++++++++++++++++++++++++
sys/arch/arm/nvidia/tegra210_carreg.h | 549 +++++++++++++
sys/arch/arm/nvidia/tegra_reg.h | 4 +-
sys/arch/evbarm/conf/TEGRA | 8 +-
7 files changed, 1938 insertions(+), 12 deletions(-)
diffs (truncated from 2048 to 300 lines):
diff -r 7d6ac7efb04d -r 5af6f2c8ec8e sys/arch/arm/nvidia/files.tegra
--- a/sys/arch/arm/nvidia/files.tegra Fri Jul 21 01:00:58 2017 +0000
+++ b/sys/arch/arm/nvidia/files.tegra Fri Jul 21 01:01:22 2017 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.40 2017/06/02 00:09:56 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.41 2017/07/21 01:01:22 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -47,11 +47,16 @@
attach tegrafuse at fdt with tegra_fuse
file arch/arm/nvidia/tegra_fuse.c tegra_fuse
-# Clock and Reset controller
+# Clock and Reset controller (T124)
device tegra124car: clk
attach tegra124car at fdt with tegra124_car
file arch/arm/nvidia/tegra124_car.c tegra124_car
+# Clock and Reset controller (T210)
+device tegra210car: clk
+attach tegra210car at fdt with tegra210_car
+file arch/arm/nvidia/tegra210_car.c tegra210_car
+
# GPIO controller
device tegragpio: gpiobus
attach tegragpio at fdt with tegra_gpio
diff -r 7d6ac7efb04d -r 5af6f2c8ec8e sys/arch/arm/nvidia/tegra124_car.c
--- a/sys/arch/arm/nvidia/tegra124_car.c Fri Jul 21 01:00:58 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra124_car.c Fri Jul 21 01:01:22 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra124_car.c,v 1.13 2017/04/29 11:00:17 jmcneill Exp $ */
+/* $NetBSD: tegra124_car.c,v 1.14 2017/07/21 01:01:22 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.13 2017/04/29 11:00:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.14 2017/07/21 01:01:22 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -427,7 +427,7 @@
{ "clk_m", NULL, "pll_u_48", NULL, "pll_p_out0", NULL, "pll_u_480" };
static struct tegra_clk tegra124_car_clocks[] = {
- CLK_FIXED("clk_m", TEGRA_REF_FREQ),
+ CLK_FIXED("clk_m", TEGRA124_REF_FREQ),
CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG,
CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP),
diff -r 7d6ac7efb04d -r 5af6f2c8ec8e sys/arch/arm/nvidia/tegra124_carreg.h
--- a/sys/arch/arm/nvidia/tegra124_carreg.h Fri Jul 21 01:00:58 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra124_carreg.h Fri Jul 21 01:01:22 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra124_carreg.h,v 1.5 2017/01/22 17:40:06 jakllsch Exp $ */
+/* $NetBSD: tegra124_carreg.h,v 1.6 2017/07/21 01:01:22 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,6 +29,8 @@
#ifndef _ARM_TEGRA124_CARREG_H
#define _ARM_TEGRA124_CARREG_H
+#define TEGRA124_REF_FREQ 12000000
+
#define CAR_RST_SOURCE_REG 0x00
#define CAR_RST_SOURCE_WDT_EN __BIT(5)
#define CAR_RST_SOURCE_WDT_SEL __BIT(4)
diff -r 7d6ac7efb04d -r 5af6f2c8ec8e sys/arch/arm/nvidia/tegra210_car.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/nvidia/tegra210_car.c Fri Jul 21 01:01:22 2017 +0000
@@ -0,0 +1,1370 @@
+/* $NetBSD: tegra210_car.c,v 1.1 2017/07/21 01:01:22 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.1 2017/07/21 01:01:22 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/rndpool.h>
+#include <sys/rndsource.h>
+#include <sys/atomic.h>
+#include <sys/kmem.h>
+
+#include <dev/clk/clk_backend.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra210_carreg.h>
+#include <arm/nvidia/tegra_clock.h>
+#include <arm/nvidia/tegra_pmcreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#include <dev/fdt/fdtvar.h>
+
+static int tegra210_car_match(device_t, cfdata_t, void *);
+static void tegra210_car_attach(device_t, device_t, void *);
+
+static struct clk *tegra210_car_clock_decode(device_t, const void *, size_t);
+
+static const struct fdtbus_clock_controller_func tegra210_car_fdtclock_funcs = {
+ .decode = tegra210_car_clock_decode
+};
+
+/* DT clock ID to clock name mappings */
+static struct tegra210_car_clock_id {
+ const char *name;
+ u_int id;
+} tegra210_car_clock_ids[] = {
+ { "ISPB", 3 },
+ { "RTC", 4 },
+ { "TIMER", 5 },
+ { "UARTA", 6 },
+ { "GPIO", 8 },
+ { "SDMMC2", 9 },
+ { "I2S1", 11 },
+ { "I2C1", 12 },
+ { "SDMMC1", 14 },
+ { "SDMMC4", 15 },
+ { "PWM", 17 },
+ { "I2S2", 18 },
+ { "USBD", 22 },
+ { "ISP", 23 },
+ { "DISP2", 26 },
+ { "DISP1", 27 },
+ { "HOST1X", 28 },
+ { "I2S0", 30 },
+ { "MC", 32 },
+ { "AHBDMA", 33 },
+ { "APBDMA", 34 },
+ { "PMC", 38 },
+ { "KFUSE", 40 },
+ { "SBC1", 41 },
+ { "SBC2", 44 },
+ { "SBC3", 46 },
+ { "I2C5", 47 },
+ { "DSIA", 48 },
+ { "CSI", 52 },
+ { "I2C2", 54 },
+ { "UARTC", 55 },
+ { "MIPI_CAL", 56 },
+ { "EMC", 57 },
+ { "USB2", 58 },
+ { "BSEV", 63 },
+ { "UARTD", 65 },
+ { "I2C3", 67 },
+ { "SBC4", 68 },
+ { "SDMMC3", 69 },
+ { "PCIE", 70 },
+ { "OWR", 71 },
+ { "AFI", 72 },
+ { "CSITE", 73 },
+ { "SOC_THERM", 78 },
+ { "DTV", 79 },
+ { "I2CSLOW", 81 },
+ { "DSIB", 82 },
+ { "TSEC", 83 },
+ { "XUSB_HOST", 89 },
+ { "CSUS", 92 },
+ { "MSELECT", 99 },
+ { "TSENSOR", 100 },
+ { "I2S3", 101 },
+ { "I2S4", 102 },
+ { "I2C4", 103 },
+ { "D_AUDIO", 106 },
+ { "APB2APE", 107 },
+ { "HDA2CODEC_2X", 111 },
+ { "SPDIF_2X", 118 },
+ { "ACTMON", 119 },
+ { "EXTERN1", 120 },
+ { "EXTERN2", 121 },
+ { "EXTERN3", 122 },
+ { "SATA_OOB", 123 },
+ { "SATA", 124 },
+ { "HDA", 125 },
+ { "HDA2HDMI", 128 },
+ { "XUSB_GATE", 143 },
+ { "CILAB", 144 },
+ { "CILCD", 145 },
+ { "CILE", 146 },
+ { "DSIALP", 147 },
+ { "DSIBLP", 148 },
+ { "ENTROPY", 149 },
+ { "XUSB_SS", 156 },
+ { "DMIC1", 161 },
+ { "DMIC2", 162 },
+ { "I2C6", 166 },
+ { "VIM2_CLK", 171 },
+ { "MIPIBIF", 173 },
+ { "CLK72MHZ", 177 },
+ { "VIC03", 178 },
+ { "DPAUX", 181 },
+ { "SOR0", 182 },
+ { "SOR1", 183 },
+ { "GPU", 184 },
+ { "DBGAPB", 185 },
+ { "PLL_P_OUT_ADSP", 187 },
+ { "PLL_G_REF", 189 },
+ { "SDMMC_LEGACY", 193 },
+ { "NVDEC", 194 },
+ { "NVJPG", 195 },
+ { "DMIC3", 197 },
+ { "APE", 198 },
+ { "MAUD", 202 },
+ { "TSECB", 206 },
+ { "DPAUX1", 207 },
+ { "VI_I2C", 208 },
+ { "HSIC_TRK", 209 },
+ { "USB2_TRK", 210 },
+ { "QSPI", 211 },
+ { "UARTAPE", 212 },
+ { "NVENC", 219 },
+ { "SOR_SAFE", 222 },
+ { "PLL_P_OUT_CPU", 223 },
+ { "UARTB", 224 },
+ { "VFIR", 225 },
+ { "SPDIF_IN", 226 },
+ { "SPDIF_OUT", 227 },
+ { "VI", 228 },
+ { "VI_SENSOR", 229 },
+ { "FUSE", 230 },
+ { "FUSE_BURN", 231 },
+ { "CLK_32K", 232 },
+ { "CLK_M", 233 },
+ { "CLK_M_DIV2", 234 },
+ { "CLK_M_DIV4", 235 },
+ { "PLL_REF", 236 },
+ { "PLL_C", 237 },
+ { "PLL_C_OUT1", 238 },
+ { "PLL_C2", 239 },
+ { "PLL_C3", 240 },
+ { "PLL_M", 241 },
+ { "PLL_M_OUT1", 242 },
+ { "PLL_P", 243 },
+ { "PLL_P_OUT1", 244 },
+ { "PLL_P_OUT2", 245 },
+ { "PLL_P_OUT3", 246 },
+ { "PLL_P_OUT4", 247 },
+ { "PLL_A", 248 },
+ { "PLL_A_OUT0", 249 },
+ { "PLL_D", 250 },
+ { "PLL_D_OUT0", 251 },
+ { "PLL_D2", 252 },
+ { "PLL_D2_OUT0", 253 },
+ { "PLL_U", 254 },
+ { "PLL_U_480M", 255 },
+ { "PLL_U_60M", 256 },
+ { "PLL_U_48M", 257 },
+ { "PLL_X", 259 },
+ { "PLL_X_OUT0", 260 },
+ { "PLL_RE_VCO", 261 },
+ { "PLL_RE_OUT", 262 },
+ { "PLL_E", 263 },
+ { "SPDIF_IN_SYNC", 264 },
+ { "I2S0_SYNC", 265 },
+ { "I2S1_SYNC", 266 },
+ { "I2S2_SYNC", 267 },
+ { "I2S3_SYNC", 268 },
+ { "I2S4_SYNC", 269 },
+ { "VIMCLK_SYNC", 270 },
+ { "AUDIO0", 271 },
+ { "AUDIO1", 272 },
+ { "AUDIO2", 273 },
+ { "AUDIO3", 274 },
+ { "AUDIO4", 275 },
+ { "SPDIF", 276 },
+ { "CLK_OUT_1", 277 },
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