Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/netbsd-8]: src/sys/dev/pci regen
details: https://anonhg.NetBSD.org/src/rev/cbab8f49098a
branches: netbsd-8
changeset: 852433:cbab8f49098a
user: martin <martin%NetBSD.org@localhost>
date: Wed Jul 17 15:29:41 2019 +0000
description:
regen
diffstat:
sys/dev/pci/pcidevs.h | 212 +-
sys/dev/pci/pcidevs_data.h | 22183 +++++++++++++++++++++---------------------
2 files changed, 11468 insertions(+), 10927 deletions(-)
diffs (truncated from 29140 to 300 lines):
diff -r f13befe7d308 -r cbab8f49098a sys/dev/pci/pcidevs.h
--- a/sys/dev/pci/pcidevs.h Wed Jul 17 15:27:55 2019 +0000
+++ b/sys/dev/pci/pcidevs.h Wed Jul 17 15:29:41 2019 +0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs.h,v 1.1281.2.14 2019/03/07 17:05:20 martin Exp $ */
+/* $NetBSD: pcidevs.h,v 1.1281.2.15 2019/07/17 15:29:41 martin Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: pcidevs,v 1.1289.2.14 2019/03/07 17:03:52 martin Exp
+ * NetBSD: pcidevs,v 1.1289.2.15 2019/07/17 15:27:55 martin Exp
*/
/*
@@ -641,6 +641,7 @@
#define PCI_VENDOR_FREESCALE 0x1957 /* Freescale Semiconductor */
#define PCI_VENDOR_ATTANSIC 0x1969 /* Attansic Technologies */
#define PCI_VENDOR_JMICRON 0x197b /* JMicron Technology */
+#define PCI_VENDOR_PHISON 0x1987 /* Phison */
#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines */
#define PCI_VENDOR_HUAWEI 0x19e5 /* Huaewi Technology */
#define PCI_VENDOR_ASPEED 0x1a03 /* ASPEED Technology */
@@ -1298,7 +1299,11 @@
#define PCI_PRODUCT_ASMEDIA_ASM1042 0x1042 /* ASM1042 USB 3.0 Host Controller */
#define PCI_PRODUCT_ASMEDIA_ASM1083 0x1080 /* ASM1083/1085 PCIe-PCI Bridge */
#define PCI_PRODUCT_ASMEDIA_ASM1042A 0x1142 /* ASM1042A USB 3.0 Host Controller */
+#define PCI_PRODUCT_ASMEDIA_ASM1182 0x1182 /* ASM1182E PCIE Bridge Controller */
+#define PCI_PRODUCT_ASMEDIA_ASM1184 0x1184 /* ASM1184E PCIE Bridge Controller */
#define PCI_PRODUCT_ASMEDIA_ASM1142 0x1242 /* ASM1142 USB 3.1 Host Controller */
+#define PCI_PRODUCT_ASMEDIA_ASM1143 0x1343 /* ASM1143 USB 3.1 Host Controller */
+#define PCI_PRODUCT_ASMEDIA_ASM2142 0x2142 /* ASM2142 USB 3.1 Host Controller */
/* Asustek products */
#define PCI_PRODUCT_ASUSTEK_HFCPCI 0x0675 /* ISDN */
@@ -1732,14 +1737,33 @@
#define PCI_PRODUCT_ATI_RADEON_HD7340 0x9808 /* Radeon HD7340 Graphics */
#define PCI_PRODUCT_ATI_RADEON_HDMI_DP_AUDIO 0x9840 /* HDMI/DP Audio */
#define PCI_PRODUCT_ATI_RADEON_R2_R3_R3E_R4 0x9854 /* Radeon R2/R3/R4 Graphics */
-#define PCI_PRODUCT_ATI_RADEON_HD2600_HD 0xaa08 /* Radeon HD2600 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD2900_HDA 0xaa00 /* Radeon HD 2900 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD3650_HDA 0xaa01 /* Radeon HD 3650/3730/3750 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD2600_HDA 0xaa08 /* Radeon HD 2600 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD2350_HDA 0xaa10 /* Radeon HD 2350PRO/2400PRO/2400XT/3410 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD3690_HDA 0xaa18 /* Radeon HD 3690/3800 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD36XX_HDA 0xaa20 /* Radeon HD 3650/3730/3750 HD Audio Controller */
#define PCI_PRODUCT_ATI_RADEON_HD34XX_HDA 0xaa28 /* Radeon HD 34xx HD Audio Controller */
-#define PCI_PRODUCT_ATI_RADEON_HD4350_HD 0xaa38 /* Radeon HD4350 HD Audio Controller */
-#define PCI_PRODUCT_ATI_RADEON_HD5600_HDMI 0xaa60 /* Redwood HDMI Audio */
-#define PCI_PRODUCT_ATI_RADEON_HD54XX_HDA 0xaa68 /* Radeon HD 54xx Audio */
-#define PCI_PRODUCT_ATI_RADEON_HD7700_HDA 0xaab0 /* Radeon HD 7700 HD Audio */
-#define PCI_PRODUCT_ATI_RADEON_RX460_HDA 0xaae0 /* Radeon RX460 HD Audio */
-#define PCI_PRODUCT_ATI_RADEON_RX470_HDA 0xaaf0 /* Radeon RX470 HD Audio */
+#define PCI_PRODUCT_ATI_RADEON_HD4850_HDA 0xaa30 /* Radeon HD 4850 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD4350_HDA 0xaa38 /* Radeon HD 4350 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD5830_HDA 0xaa50 /* Radeon HD 5830/5850/5870/6850/6870 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD5700_HDA 0xaa58 /* Radeon HD 5700 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD5000_HDA 0xaa60 /* Radeon HD 5000 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD68XX_HDA 0xaa68 /* Radeon HD 5400/6300/7300 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD6930_HDA 0xaa80 /* Radeon HD 6930/6950/6970/6990 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD6790_HDA 0xaa88 /* Radeon HD 6790/6850/6870/7720 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD6500_HDA 0xaa90 /* Radeon HD 6500/6600/6700M HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD6450_HDA 0xaa98 /* Radeon HD 6450/7450/8450/8490, R5 230/235/235X HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD7870_HDA 0xaaa0 /* Radeon HD 7870XT/7950/7970 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_HD7700_HDA 0xaab0 /* Radeon HD 7700 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_R7_360_HDA 0xaac0 /* Radeon R7 360, R9 360 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_R9_290_HDA 0xaac8 /* Radeon R9 290/290X, 390/390X HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_R9_285_HDA 0xaad8 /* Radeon R9 285/380 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_RX_460_HDA 0xaae0 /* Radeon RX 460/550/640SP, RX 560/560X HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_RX_550_HDA 0xaae8 /* Radeon R9 Nano, FURY HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_RX_470_HDA 0xaaf0 /* Radeon RX 470/480/570/580/590 HD Audio Controller */
+#define PCI_PRODUCT_ATI_RADEON_VEGA56_HDA 0xaaf8 /* Radeon Vega 56/64 */
+#define PCI_PRODUCT_ATI_RADEON_RX_550_HDA2 0xab00 /* Radeon RX 550/640SP/560/560X HD Audio Controller */
/* Auravision products */
#define PCI_PRODUCT_AURAVISION_VXP524 0x01f7 /* VxP524 PCI Video Processor */
@@ -2761,17 +2785,25 @@
#define PCI_PRODUCT_MARVELL_MV78460 0x7846 /* MV78460 SoC Armada XP */
#define PCI_PRODUCT_MARVELL_88W8660 0x8660 /* 88W8660 SoC Orion1 */
-#define PCI_PRODUCT_MARVELL2_88SE9120 0x9120 /* 88SE9120 SATA */
-#define PCI_PRODUCT_MARVELL2_88SE912X 0x9123 /* 88SE912[38] SATA II or III PCI-E AHCI Controller */
-#define PCI_PRODUCT_MARVELL2_88SE9125 0x9125 /* 88SE9125 SATA III PCI-E AHCI Controller */
-#define PCI_PRODUCT_MARVELL2_88SE9172 0x9172 /* 88SE9172 SATA */
-#define PCI_PRODUCT_MARVELL2_88SE9182 0x9182 /* 88SE9182 SATA */
-#define PCI_PRODUCT_MARVELL2_88SE9183 0x9183 /* 88SE9183 SATA */
-#define PCI_PRODUCT_MARVELL2_88SE91XX 0x91a3 /* 88SE91XX SATA */
-#define PCI_PRODUCT_MARVELL2_88SE9215 0x9215 /* 88SE9215 SATA */
-#define PCI_PRODUCT_MARVELL2_88SE9220 0x9220 /* 88SE9220 SATA */
-#define PCI_PRODUCT_MARVELL2_88SE9230 0x9230 /* 88SE9230 SATA */
-#define PCI_PRODUCT_MARVELL2_88SE9235 0x9235 /* 88SE9235 SATA */
+#define PCI_PRODUCT_MARVELL2_88SE9120 0x9120 /* 88SE9120 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE912X 0x9123 /* 88SE912[38] SATA II or III PCI-E Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9125 0x9125 /* 88SE9125 SATA III PCI-E Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9128 0x9128 /* 88SE9128 SATA III PCI-E Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9130 0x9130 /* 88SE9130 SATA III PCI-E Controller with HyperDuo */
+#define PCI_PRODUCT_MARVELL2_88SE9172 0x9172 /* 88SE9172 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9170 0x9178 /* 88SE9170 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9172_2 0x917a /* 88SE9170 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9182 0x9182 /* 88SE9182 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9183 0x9183 /* 88SE9183 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE91XX 0x91a3 /* 88SE91XX SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE912X_2 0x91a4 /* 88SE912X IDE Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9215 0x9215 /* 88SE9215 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9220 0x9220 /* 88SE9220 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9230 0x9230 /* 88SE9230 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9235 0x9235 /* 88SE9235 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9445 0x9445 /* 88SE9445 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9480 0x9480 /* 88SE9480 SATA Controller */
+#define PCI_PRODUCT_MARVELL2_88SE9485 0x9485 /* 88SE9485 SATA Controller */
/* Micro-star International Co Ltd */
#define PCI_PRODUCT_MSI_RT3090 0x891a /* MIS RT3090 */
@@ -3505,12 +3537,13 @@
#define PCI_PRODUCT_INTEL_I218_LM3 0x15a2 /* I218-LM Ethernet Connection */
#define PCI_PRODUCT_INTEL_I218_V3 0x15a3 /* I218-V Ethernet Connection */
#define PCI_PRODUCT_INTEL_X552_VF 0x15a8 /* X552 VF */
-#define PCI_PRODUCT_INTEL_X552_VF_HV 0x15a9 /* X552 VF */
+#define PCI_PRODUCT_INTEL_X552_VF_HV 0x15a9 /* X552 VF (Hyper-V) */
#define PCI_PRODUCT_INTEL_X552_KX4 0x15aa /* X552 KX4 */
#define PCI_PRODUCT_INTEL_X552_KR 0x15ab /* X552 KR */
#define PCI_PRODUCT_INTEL_X552_SFP 0x15ac /* X552 SFP+ */
#define PCI_PRODUCT_INTEL_X557_AT2 0x15ad /* X557-AT2 */
#define PCI_PRODUCT_INTEL_X552_1G_T 0x15ae /* X552 1000Base-T */
+#define PCI_PRODUCT_INTEL_X552_XFI 0x15b0 /* X552 XFI */
#define PCI_PRODUCT_INTEL_C3K_X553_VF_HYPV 0x15b4 /* C3000 X553 VF (Hyper-V) */
#define PCI_PRODUCT_INTEL_I219_LM2 0x15b7 /* I219-LM Ethernet Connection */
#define PCI_PRODUCT_INTEL_I219_V2 0x15b8 /* I219-V Ethernet Connection */
@@ -3526,6 +3559,8 @@
#define PCI_PRODUCT_INTEL_C3K_X553_SGMII_BP 0x15c6 /* C3000 X553 1GbE SGMII Backplane (10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_SGMII_BP_L 0x15c7 /* C3000 X553 1GbE SGMII Backplane (non-10G SKU) */
#define PCI_PRODUCT_INTEL_C3K_X553_10G_T 0x15c8 /* C3000 X553 10GBASE-T (X557) */
+#define PCI_PRODUCT_INTEL_C3K_X553_QSFP 0x15ca /* C3000 X553 10G QSFP */
+#define PCI_PRODUCT_INTEL_C3K_X553_QSFP_N 0x15cc /* C3000 X553 10G QSFP */
#define PCI_PRODUCT_INTEL_C3K_X553_KR_SFP 0x15ce /* C3000 X553 10G SFP+ (KR) */
#define PCI_PRODUCT_INTEL_X550T1 0x15d1 /* X550 10G Ethernet */
#define PCI_PRODUCT_INTEL_I219_V5 0x15d6 /* I219-V Ethernet Connection */
@@ -3815,6 +3850,10 @@
#define PCI_PRODUCT_INTEL_C2000_SGMII 0x1f41 /* C2000 Ethernet(SGMII) */
#define PCI_PRODUCT_INTEL_C2000_DUMMYGBE 0x1f42 /* C2000 Ethernet(Dummy function) */
#define PCI_PRODUCT_INTEL_C2000_25GBE 0x1f45 /* C2000 Ethernet(2.5Gbe) */
+#define PCI_PRODUCT_INTEL_XEONSC_UBOX_0 0x2014 /* Xeon Scalable Ubox */
+#define PCI_PRODUCT_INTEL_XEONSC_UBOX_1 0x2016 /* Xeon Scalable Ubox */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_0 0x2080 /* Xeon Scalable PCU */
+#define PCI_PRODUCT_INTEL_XEONSC_PCU_1 0x2082 /* Xeon Scalable PCU */
#define PCI_PRODUCT_INTEL_BSW_HB 0x2280 /* Braswell Soc Transaction Router */
#define PCI_PRODUCT_INTEL_BSW_HDA 0x2284 /* Braswell HD Audio */
#define PCI_PRODUCT_INTEL_BSW_SIO_DMA_2 0x2286 /* Braswell SIO DMA */
@@ -4376,26 +4415,39 @@
#define PCI_PRODUCT_INTEL_XE7_V4_QPI_LINK2 0x2f40 /* Xeon E7 v4 QPI Link 2 */
#define PCI_PRODUCT_INTEL_XE7_V4_RQPI_RING 0x2f41 /* Xeon E7 v4 QPI Ring Interface */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC1_MAIN 0x2f68 /* Xeon E5 v3 IMC Main */
+#define PCI_PRODUCT_INTEL_XE5_V3_HA1 0x2f60 /* Xeon E7 v3/Xeon E5 v3/Core i7 Home Agent 1 */
+#define PCI_PRODUCT_INTEL_XE5_V3_ICM1_TATRR 0x2f68 /* Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Target Address, Thermal & RAS Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC1_TADR1 0x2f6a /* Xeon E5 v3 IMC Ch 0-1 Target Address Decode Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC1_TADR2 0x2f6b /* Xeon E5 v3 IMC Ch 0-1 Target Address Decode Registers */
#define PCI_PRODUCT_INTEL_XE7_V4_IMC1_TADR3 0x2f6c /* Xeon E7 v4 IMC Ch 0-3 Target Address Decoder */
#define PCI_PRODUCT_INTEL_XE7_V4_IMC1_TADR4 0x2f6d /* Xeon E7 v4 IMC Ch 0-3 Target Address Decoder */
+#define PCI_PRODUCT_INTEL_XE5_V3_DDRIO_CHAN2 0x2f6e /* Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO Channel 2/3 Broadcast */
+#define PCI_PRODUCT_INTEL_XE5_V3_DDRIO_BROAD2 0x2f6f /* Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO Global Broadcast */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_RAS 0x2f71 /* Xeon E5 v3 IMC RAS Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC1_RAS 0x2f79 /* Xeon E5 v3 IMC Ras Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_UBOX_2 0x2f7d /* Xeon E5 v3 Scratchpad and Semaphores */
#define PCI_PRODUCT_INTEL_XE5_V3_QPI_LINK0 0x2f80 /* Xeon E5 v3 QPI Link 0 */
#define PCI_PRODUCT_INTEL_XE5_V3_RQPI_RING 0x2f81 /* Xeon E5 v3/Core i7-6xxxK QPI Ring Interface */
#define PCI_PRODUCT_INTEL_XE5_V3_QPI_LINK4 0x2f83 /* Xeon E5 v3 QPI Link 0 */
+#define PCI_PRODUCT_INTEL_XE5_V3_QPIL0D1 0x2f85 /* Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 Debug */
+#define PCI_PRODUCT_INTEL_XE5_V3_QPIL0D2 0x2f86 /* Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 Debug */
+#define PCI_PRODUCT_INTEL_XE5_V3_QPIL0D3 0x2f87 /* Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 Debug */
+#define PCI_PRODUCT_INTEL_XE5_V3_VCU1 0x2f88 /* Xeon E7 v3/Xeon E5 v3/Core i7 VCU */
+#define PCI_PRODUCT_INTEL_XE5_V3_VCU2 0x2f8a /* Xeon E7 v3/Xeon E5 v3/Core i7 VCU */
#define PCI_PRODUCT_INTEL_XE5_V3_QPI_LINK1 0x2f90 /* Xeon E5 v3 QPI Link 1 */
#define PCI_PRODUCT_INTEL_XE5_V3_PCU_1 0x2f98 /* Xeon E5 v3 Power Control Unit */
#define PCI_PRODUCT_INTEL_XE5_V3_PCU_2 0x2f99 /* Xeon E5 v3 Power Control Unit */
#define PCI_PRODUCT_INTEL_XE5_V3_PCU_3 0x2f9a /* Xeon E5 v3 Power Control Unit */
#define PCI_PRODUCT_INTEL_XE5_V3_PCU_5 0x2f9c /* Xeon E5 v3 Power Control Unit */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_MAIN 0x2fa8 /* Xeon E5 v3 IMC Main */
+#define PCI_PRODUCT_INTEL_XE5_V3_HA0 0x2fa0 /* Xeon E7 v3/Xeon E5 v3/Core i7 Home Agent 0 */
+#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_TATRR 0x2fa8 /* Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Target Address, Thermal & RAS Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_TADR1 0x2faa /* Xeon E5 v3 IMC Ch 0-1 Target Address Decode Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_TADR2 0x2fab /* Xeon E5 v3 IMC Ch 0-1 Target Address Decode Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_TADR3 0x2fac /* Xeon E5 v3 IMC Ch 2-3 Target Address Decode Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_TADR4 0x2fad /* Xeon E5 v3 IMC Ch 2-3 Target Address Decode Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_DDRIO_CHAN 0x2fae /* Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO Channel 0/1 Broadcast */
+#define PCI_PRODUCT_INTEL_XE5_V3_DDRIO_BROAD 0x2faf /* Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO Global Broadcast */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_REG1 0x2fb0 /* Xeon E5 v3 IMC Ch 0-1 Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_REG2 0x2fb1 /* Xeon E5 v3 IMC Ch 0-1 Registers */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_REG3 0x2fb2 /* Xeon E5 v3 IMC Ch 2-3 Registers */
@@ -4425,6 +4477,37 @@
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_DDRIO_A 0x2fd9 /* Xeon E5 v3 IMC DDRIO */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_DDRIO_B 0x2fda /* Xeon E5 v3 IMC DDRIO */
#define PCI_PRODUCT_INTEL_XE5_V3_IMC0_DDRIO_C 0x2fdb /* Xeon E5 v3 IMC DDRIO */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG1 0x2fe0 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG2 0x2fe1 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG3 0x2fe2 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG4 0x2fe3 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG5 0x2fe4 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG6 0x2fe5 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG7 0x2fe6 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG8 0x2fe7 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG9 0x2fe8 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG10 0x2fe9 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG11 0x2fea /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG12 0x2feb /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG13 0x2fec /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG14 0x2fed /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG15 0x2fee /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG16 0x2fef /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG17 0x2ff0 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG18 0x2ff1 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG19 0x2ff2 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG20 0x2ff3 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG21 0x2ff4 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG22 0x2ff5 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG23 0x2ff6 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_UC_REG24 0x2ff7 /* Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_BRA1 0x2ff8 /* Xeon E7 v3/Xeon E5 v3/Core i7 Buffered Ring Agent */
+#define PCI_PRODUCT_INTEL_XE5_V3_BRA2 0x2ff9 /* Xeon E7 v3/Xeon E5 v3/Core i7 Buffered Ring Agent */
+#define PCI_PRODUCT_INTEL_XE5_V3_BRA3 0x2ffa /* Xeon E7 v3/Xeon E5 v3/Core i7 Buffered Ring Agent */
+#define PCI_PRODUCT_INTEL_XE5_V3_BRA4 0x2ffb /* Xeon E7 v3/Xeon E5 v3/Core i7 Buffered Ring Agent */
+#define PCI_PRODUCT_INTEL_XE5_V3_SADBR1 0x2ffc /* Xeon E7 v3/Xeon E5 v3/Core i7 System Address Decoder & Broadcast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_SADBR2 0x2ffd /* Xeon E7 v3/Xeon E5 v3/Core i7 System Address Decoder & Broadcast Registers */
+#define PCI_PRODUCT_INTEL_XE5_V3_SADBR3 0x2ffe /* Xeon E7 v3/Xeon E5 v3/Core i7 System Address Decoder & Broadcast Registers */
#define PCI_PRODUCT_INTEL_WIFI_LINK_3165_1 0x3165 /* Dual Band Wireless AC 3165 */
#define PCI_PRODUCT_INTEL_WIFI_LINK_3165_2 0x3166 /* Dual Band Wireless AC 3165 */
#define PCI_PRODUCT_INTEL_GLK_IGD_1 0x3184 /* UHD Graphics 605 */
@@ -4704,8 +4787,18 @@
#define PCI_PRODUCT_INTEL_E5_SAD_1 0x3cf4 /* E5 SAD */
#define PCI_PRODUCT_INTEL_E5_BROADCAST 0x3cf5 /* E5 Broadcast */
#define PCI_PRODUCT_INTEL_E5_SAD_2 0x3cf6 /* E5 SAD */
+#define PCI_PRODUCT_INTEL_XEONE_S_D_HOST_DRAM_2C 0x3e0f /* Xeon E (S, Desktop) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_H_HOST_DRAM_4C 0x3e10 /* Xeon E (H) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_S_W_HOST_DRAM_4C 0x3e18 /* Xeon E (S, WS) Host Bridge, DRAM */
#define PCI_PRODUCT_INTEL_CORE8G_S_HOST_DRAM_4C 0x3e1f /* Core 8G (S) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_CORE8G_U_HOST_DRAM_4C 0x3e34 /* Core 8G (U) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_CORE8G_U_HOST_DRAM_2C 0x3e35 /* Core 8G (U) Host Bridge, DRAM */
#define PCI_PRODUCT_INTEL_CORE8G_S_HOST_DRAM_6C 0x3ec2 /* Core 8G (S) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_S_D_HOST_DRAM_8C 0x3e30 /* Xeon E (S, Desktop) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_S_W_HOST_DRAM_8C 0x3e31 /* Xeon E (S, WS) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_S_S_HOST_DRAM_8C 0x3e32 /* Xeon E (S, Server) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_S_S_HOST_DRAM_4C 0x3e33 /* Xeon E (S, Server) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_H_HOST_DRAM_6C 0x3e4c /* Xeon E (H) Host Bridge, DRAM */
#define PCI_PRODUCT_INTEL_CORE8G_PCIE_X16 0x3e81 /* Core 8G (S) PCIe x16 */
#define PCI_PRODUCT_INTEL_CORE8G_PCIE_X8 0x3e85 /* Core 8G (S) PCIe x16 */
#define PCI_PRODUCT_INTEL_CORE8G_PCIE_X4 0x3e89 /* Core 8G (S) PCIe x16 */
@@ -4713,8 +4806,17 @@
#define PCI_PRODUCT_INTEL_COFLK_IGD_2 0x3e91 /* UHD Graphics 630 */
#define PCI_PRODUCT_INTEL_COFLK_IGD_3 0x3e92 /* UHD Graphics 630 */
#define PCI_PRODUCT_INTEL_COFLK_IGD_4 0x3e93 /* UHD Graphics 610 */
+#define PCI_PRODUCT_INTEL_XEONE_IGD 0x3e96 /* UHD Graphics P630 */
#define PCI_PRODUCT_INTEL_COFLK_IGD_5 0x3e9b /* UHD Graphics 630 */
+#define PCI_PRODUCT_INTEL_WHISKYLK_IGD_1 0x3ea0 /* UHD Graphics 620 */
+#define PCI_PRODUCT_INTEL_WHISKYLK_IGD_2 0x3ea1 /* UHD Graphics 610 */
#define PCI_PRODUCT_INTEL_COFLK_IGD_6 0x3ea5 /* Iris Plus Graphics 655 */
+#define PCI_PRODUCT_INTEL_XEONE_S_D_HOST_DRAM_6C 0x3ec2 /* Xeon E (S, Desktop) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_CORE8G_H_H_HOST_DRAM_6C 0x3ec4 /* Core 8G (H, Halo) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_S_W_HOST_DRAM_6C 0x3ec6 /* Xeon E (S, WS) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_S_S_HOST_DRAM_6C 0x3eca /* Xeon E (S, Server) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_U_HOST_DRAM_2C 0x3ecc /* Xeon E (U) Host Bridge, DRAM */
+#define PCI_PRODUCT_INTEL_XEONE_U_HOST_DRAM_4C 0x3ed0 /* Xeon E (U) Host Bridge, DRAM */
#define PCI_PRODUCT_INTEL_5400_HB 0x4000 /* 5400 Host */
#define PCI_PRODUCT_INTEL_5400A_HB 0x4001 /* 5400A Host */
#define PCI_PRODUCT_INTEL_5400B_HB 0x4003 /* 5400B Host */
@@ -5349,6 +5451,9 @@
#define PCI_PRODUCT_INTEL_C620_LPC_6 0xa1c6 /* C627 LPC or eSPI */
#define PCI_PRODUCT_INTEL_C620_LPC_7 0xa1c7 /* C628 LPC or eSPI */
#define PCI_PRODUCT_INTEL_C620_LPC_8 0xa1ca /* C629 LPC or eSPI */
+#define PCI_PRODUCT_INTEL_C620_LPC_9 0xa1cb /* C621A LPC or eSPI */
+#define PCI_PRODUCT_INTEL_C620_LPC_10 0xa1cc /* C627A LPC or eSPI */
+#define PCI_PRODUCT_INTEL_C620_LPC_11 0xa1cd /* C629A LPC or eSPI */
#define PCI_PRODUCT_INTEL_C620_SSATA_AHCI 0xa1d2 /* C620 sSATA AHCI */
#define PCI_PRODUCT_INTEL_C620_SSATA_RAID 0xa1d6 /* C620 sSATA 3rd Party RAID */
#define PCI_PRODUCT_INTEL_C620_PCIE_16 0xa1e7 /* C620 PCIe Root Port */
@@ -5398,6 +5503,9 @@
#define PCI_PRODUCT_INTEL_C620_LPC_S_3 0xa244 /* C621 LPC or eSPI */
#define PCI_PRODUCT_INTEL_C620_LPC_S_4 0xa245 /* C627 LPC or eSPI */
#define PCI_PRODUCT_INTEL_C620_LPC_S_5 0xa246 /* C628 LPC or eSPI */
+#define PCI_PRODUCT_INTEL_C620_LPC_S_6 0xa24a /* C621A LPC or eSPI */
+#define PCI_PRODUCT_INTEL_C620_LPC_12 0xa24b /* C627A LPC or eSPI */
+#define PCI_PRODUCT_INTEL_C620_LPC_13 0xa24c /* C629A LPC or eSPI */
#define PCI_PRODUCT_INTEL_C620_SSATA_AHCI_S 0xa252 /* C620 sSATA AHCI */
#define PCI_PRODUCT_INTEL_C620_SSATA_RAID_S 0xa256 /* C620 sSATA 3rd Party RAID */
#define PCI_PRODUCT_INTEL_C620_PCIE_S_16 0xa267 /* C620 PCIe Root Port */
@@ -5900,6 +6008,10 @@
#define PCI_PRODUCT_PHILIPS_SAA7135HL 0x7135 /* SAA7135HL PCI A/V Broadcast Decoder */
#define PCI_PRODUCT_PHILIPS_SAA7146AH 0x7146 /* SAA7146AH PCI Multimedia Bridge */
+/* Phison products */
+#define PCI_PRODUCT_PHISON_PS5000 0x5000 /* PS5000 */
+#define PCI_PRODUCT_PHISON_PS5016 0x5016 /* PS5016 */
+
/* NCR/Symbios Logic products */
#define PCI_PRODUCT_SYMBIOS_810 0x0001 /* 53c810 */
#define PCI_PRODUCT_SYMBIOS_820 0x0002 /* 53c820 */
@@ -6488,9 +6600,23 @@
#define PCI_PRODUCT_NVIDIA_GEFORCE_610M2 0x1059 /* GeForce 610M */
#define PCI_PRODUCT_NVIDIA_GT610M 0x105A /* GeForce GT 610M */
#define PCI_PRODUCT_NVIDIA_GF116 0x1244 /* GeForce GTX 550 Ti */
+#define PCI_PRODUCT_NVIDIA_GF_GTX960 0x1401 /* GeForce GTX 960 */
Home |
Main Index |
Thread Index |
Old Index