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[src/trunk]: src/sys/arch/arm/allwinner add some extra A31 registers



details:   https://anonhg.NetBSD.org/src/rev/32f992bd8506
branches:  trunk
changeset: 803007:32f992bd8506
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Fri Oct 10 23:50:43 2014 +0000

description:
add some extra A31 registers

diffstat:

 sys/arch/arm/allwinner/awin_board.c |  23 +++++++++++------------
 sys/arch/arm/allwinner/awin_reg.h   |  29 +++++++++++++++++++++++------
 sys/arch/arm/allwinner/awin_var.h   |  12 ++++++------
 3 files changed, 40 insertions(+), 24 deletions(-)

diffs (135 lines):

diff -r 4a1d442c14d9 -r 32f992bd8506 sys/arch/arm/allwinner/awin_board.c
--- a/sys/arch/arm/allwinner/awin_board.c       Fri Oct 10 22:06:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_board.c       Fri Oct 10 23:50:43 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: awin_board.c,v 1.21 2014/10/10 07:36:11 jmcneill Exp $ */
+/*     $NetBSD: awin_board.c,v 1.22 2014/10/10 23:50:43 jmcneill Exp $ */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -35,7 +35,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.21 2014/10/10 07:36:11 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.22 2014/10/10 23:50:43 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -175,7 +175,7 @@
        error = bus_space_map(&awin_bs_tag, AWIN_CORE_PBASE,
            AWIN_CORE_SIZE, 0, &awin_core_bsh);
        if (error)
-               panic("%s: failed to map a[12]0 %s registers: %d",
+               panic("%s: failed to map awin %s registers: %d",
                    __func__, "io", error);
        KASSERT(awin_core_bsh == iobase);
 
@@ -197,16 +197,15 @@
 
 #ifdef VERBOSE_INIT_ARM
        if (awin_chip_id() == AWIN_CHIP_ID_A31) {
-               uint32_t s0 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
-                   AWIN_A31_CPUCFG_OFFSET + AWIN_A31_CPUCFG_CPU0_STATUS_REG);
-               uint32_t s1 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
-                   AWIN_A31_CPUCFG_OFFSET + AWIN_A31_CPUCFG_CPU1_STATUS_REG);
-               uint32_t s2 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
-                   AWIN_A31_CPUCFG_OFFSET + AWIN_A31_CPUCFG_CPU2_STATUS_REG);
-               uint32_t s3 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
-                   AWIN_A31_CPUCFG_OFFSET + AWIN_A31_CPUCFG_CPU3_STATUS_REG);
+               uint32_t s[4];
+               unsigned int cpuno;
+               for (cpuno = 0; cpuno < 4; cpuno++) {
+                       s[cpuno] = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
+                           AWIN_A31_CPUCFG_OFFSET +
+                           AWIN_A31_CPUCFG_STATUS_REG(cpuno));
+               }
                printf("%s: cpu status: 0=%#x 1=%#x 2=%#x 3=%#x\n", __func__,
-                   s0, s1, s2, s3);
+                   s[0], s[1], s[2], s[3]);
        } else {
                uint32_t s0 = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
                    AWIN_CPUCFG_OFFSET + AWIN_CPUCFG_CPU0_STATUS_REG);
diff -r 4a1d442c14d9 -r 32f992bd8506 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Fri Oct 10 22:06:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Fri Oct 10 23:50:43 2014 +0000
@@ -169,6 +169,12 @@
 #define AWIN_SRAM_VER_BOOT_SEL_PAD_STA __BIT(8)
 #define AWIN_SRAM_VER_BITS             __BITS(7,0)
 
+#define AWIN_SRAM_VER_KEY_A10          0x1623
+#define AWIN_SRAM_VER_KEY_A13          0x1625
+#define AWIN_SRAM_VER_KEY_A31          0x1633
+#define AWIN_SRAM_VER_KEY_A23          0x1650
+#define AWIN_SRAM_VER_KEY_A20          0x1651
+
 /* A10/A20 DRAM Controller */
 #define AWIN_DRAM_CCR_REG              0x0000
 #define AWIN_DRAM_DCR_REG              0x0004
@@ -1694,11 +1700,27 @@
 #define AWIN_A31_USB1_OFFSET           0x0001a000      /* EHCI0/OHCI0 */
 #define AWIN_A31_USB2_OFFSET           0x0001b000      /* EHCI1/OHCI1 */
 #define AWIN_A31_USB3_OFFSET           0x0001b000      /* OHCI2 */
+#define AWIN_A31_PRCM_OFFSET           0x00301400      /* PRCM */
+#define AWIN_A31_CPUCFG_OFFSET         0x00301C00
 
-#define AWIN_A31_CPUCFG_OFFSET         0x00031C00
+#define AWIN_A31_PRCM_PWROFF_GATING_REG                0x100
+#define AWIN_A31_PRCM_CPUX_PWR_CLAMP_REG       0x0140
+#define AWIN_A31_PRCM_CPU1_PWR_CLAMP_REG       0x0144
+#define AWIN_A31_PRCM_CPU2_PWR_CLAMP_REG       0x0148
+#define AWIN_A31_PRCM_CPU3_PWR_CLAMP_REG       0x014C
+
+#define AWIN_A31_CPUCFG_CPU0_RST_CTRL_REG      0x0040
+#define AWIN_A31_CPUCFG_CPU0_PWR_CLAMP_STATUS_REG 0x0064
+#define AWIN_A31_CPUCFG_RST_CTRL_REG(n)                (0x0040 + (n * 0x40))
+#define AWIN_A31_CPUCFG_CTRL_REG(n)            (0x0044 + (n * 0x40))
+#define AWIN_A31_CPUCFG_STATUS_REG(n)          (0x0048 + (n * 0x40))
+#define AWIN_A31_CPUCFG_PWR_CLAMP_STATUS_REG(n)        (0x0064 + (n * 0x40))
 
 #define AWIN_A31_CPU_AXI_CFG_REG               0x0050
 
+#define AWIN_A31_CPUCFG_RST_CTRL_CORE_RESET __BIT(1)
+#define AWIN_A31_CPUCFG_RST_CTRL_CPU_RESET __BIT(0)
+
 #define AWIN_A31_AHB_GATING0_USB_OHCI2 __BIT(31)
 #define AWIN_A31_AHB_GATING0_USB_OHCI1 __BIT(30)
 #define AWIN_A31_AHB_GATING0_USB_OHCI0 __BIT(29)
@@ -1716,11 +1738,6 @@
 #define AWIN_A31_USB_CLK_PHY1_ENABLE   __BIT(1)
 #define AWIN_A31_USB_CLK_PHY0_ENABLE   __BIT(0)
 
-#define AWIN_A31_CPUCFG_CPU0_STATUS_REG        0x0048
-#define AWIN_A31_CPUCFG_CPU1_STATUS_REG        0x0088
-#define AWIN_A31_CPUCFG_CPU2_STATUS_REG        0x00C8
-#define AWIN_A31_CPUCFG_CPU3_STATUS_REG        0x00108
-
 #define AWIN_A31_WDOG1_IRQ_EN_REG              0x00A0
 #define AWIN_A31_WDOG1_IRQ_STA_REG             0x00A4
 #define AWIN_A31_WDOG1_CTRL_REG                        0x00B0
diff -r 4a1d442c14d9 -r 32f992bd8506 sys/arch/arm/allwinner/awin_var.h
--- a/sys/arch/arm/allwinner/awin_var.h Fri Oct 10 22:06:33 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_var.h Fri Oct 10 23:50:43 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_var.h,v 1.16 2014/09/11 02:16:15 jmcneill Exp $ */
+/* $NetBSD: awin_var.h,v 1.17 2014/10/10 23:50:43 jmcneill Exp $ */
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -94,11 +94,11 @@
 void   awin_pll7_enable(void);
 void   awin_cpu_hatch(struct cpu_info *);
 
-#define AWIN_CHIP_ID_A10       0x1623
-#define AWIN_CHIP_ID_A13       0x1625
-#define AWIN_CHIP_ID_A31       0x1633
-#define AWIN_CHIP_ID_A23       0x1650
-#define AWIN_CHIP_ID_A20       0x1651
+#define AWIN_CHIP_ID_A10       AWIN_SRAM_VER_KEY_A10
+#define AWIN_CHIP_ID_A13       AWIN_SRAM_VER_KEY_A13
+#define AWIN_CHIP_ID_A31       AWIN_SRAM_VER_KEY_A31
+#define AWIN_CHIP_ID_A23       AWIN_SRAM_VER_KEY_A23
+#define AWIN_CHIP_ID_A20       AWIN_SRAM_VER_KEY_A20
 uint16_t awin_chip_id(void);
 const char *awin_chip_name(void);
 



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