[src/trunk]: src Support prefetch size.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a745e74be24a
branches:  trunk
changeset: 790955:a745e74be24a
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Oct 28 05:41:49 2013 +0000

description:
Support prefetch size.

diffstat:

 sys/arch/x86/include/cacheinfo.h |  13 ++++++++++---
 usr.sbin/cpuctl/arch/i386.c      |  10 ++++++++--
 2 files changed, 18 insertions(+), 5 deletions(-)

diffs (73 lines):

diff -r 05680d09b232 -r a745e74be24a sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h  Mon Oct 28 05:37:24 2013 +0000
+++ b/sys/arch/x86/include/cacheinfo.h  Mon Oct 28 05:41:49 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cacheinfo.h,v 1.16 2013/09/14 17:21:19 msaitoh Exp $   */
+/*     $NetBSD: cacheinfo.h,v 1.17 2013/10/28 05:41:49 msaitoh Exp $   */
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -8,7 +8,10 @@
        uint8_t         cai_desc;
        uint8_t         cai_associativity;
        u_int           cai_totalsize; /* #entries for TLB, bytes for cache */
-       u_int           cai_linesize;   /* or page size for TLB */
+       u_int           cai_linesize;   /*
+                                        * or page size for TLB,
+                                        * or prefetch size
+                                        */
 #ifndef _KERNEL
        const char      *cai_string;
 #endif
@@ -32,8 +35,9 @@
 #define CAI_L2_DTLB2   15              /* L2 Data TLB (2/4M pages) */
 #define CAI_L2_STLB    16              /* Shared L2 TLB (4K pages) */
 #define CAI_L2_STLB2   17              /* Shared L2 TLB (4K/2M pages) */
+#define CAI_PREFETCH   18              /* Prefetch */
 
-#define        CAI_COUNT       18
+#define        CAI_COUNT       19
 
 /*
  * AMD Cache Info:
@@ -319,6 +323,9 @@
 __CI_TBL(CAI_L3CACHE,  0xea,   24,12 * 1024 * 1024, 64, NULL), \
 __CI_TBL(CAI_L3CACHE,  0xeb,   24,18 * 1024 * 1024, 64, NULL), \
 __CI_TBL(CAI_L3CACHE,  0xec,   24,24 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_PREFETCH, 0xf0,    0,               0, 64, NULL), \
+__CI_TBL(CAI_PREFETCH, 0xf1,    0,               0,128, NULL), \
+/* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
 __CI_TBL(0,               0,    0,               0,  0, NULL)  \
 }
 
diff -r 05680d09b232 -r a745e74be24a usr.sbin/cpuctl/arch/i386.c
--- a/usr.sbin/cpuctl/arch/i386.c       Mon Oct 28 05:37:24 2013 +0000
+++ b/usr.sbin/cpuctl/arch/i386.c       Mon Oct 28 05:41:49 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i386.c,v 1.45 2013/10/21 06:33:11 msaitoh Exp $        */
+/*     $NetBSD: i386.c,v 1.46 2013/10/28 05:41:49 msaitoh Exp $        */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.45 2013/10/21 06:33:11 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.46 2013/10/28 05:41:49 msaitoh Exp $");
 #endif /* not lint */
 
 #include <sys/types.h>
@@ -2005,6 +2005,12 @@
                if (sep != NULL)
                        aprint_verbose("\n");
        }
+       if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) {
+               aprint_verbose_dev(ci->ci_dev, "%dB prefetching",
+                       ci->ci_cinfo[CAI_PREFETCH].cai_linesize);
+               if (sep != NULL)
+                       aprint_verbose("\n");
+       }
        if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) {
                sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL);
                sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep);