[src/trunk]: src/sys/arch/x86/include Correct the comment about the extended ...

[dsl <dsl%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6bc307d628c2
branches:  trunk
changeset: 783745:6bc307d628c2
user:      dsl <dsl%NetBSD.org@localhost>
date:      Sun Jan 06 22:37:36 2013 +0000

description:
Correct the comment about the extended family and model bits.
Add some definitions related to the process extended state enumeration.

diffstat:

 sys/arch/x86/include/specialreg.h |  32 ++++++++++++++++++++++++++++++--
 1 files changed, 30 insertions(+), 2 deletions(-)

diffs (53 lines):

diff -r 0398a471ddc4 -r 6bc307d628c2 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Sun Jan 06 22:06:00 2013 +0000
+++ b/sys/arch/x86/include/specialreg.h Sun Jan 06 22:37:36 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.61 2013/01/03 23:03:57 dsl Exp $      */
+/*     $NetBSD: specialreg.h,v 1.62 2013/01/06 22:37:36 dsl Exp $      */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -336,7 +336,13 @@
 #define CPUID2MODEL(cpuid)     (((cpuid) >> 4) & 0xf)
 #define CPUID2STEPPING(cpuid)  ((cpuid) & 0xf)
 
-/* Extended family and model are defined on amd64 processors */
+/*
+ * The Extended family bits should only be inspected when CPUID2FAMILY()
+ * returns 15. They are use to encode family value 16 to 270 (add 15).
+ * The Extended model hits are the high 4 bits of the model.
+ * They are only valid for family >= 15 or family 6 (intel, but all amd
+ * family 6 are documented to return zero bits for them).
+ */
 #define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
 #define CPUID2EXTMODEL(cpuid)  (((cpuid) >> 16) & 0xf)
 
@@ -359,6 +365,28 @@
        "\1" "x87"      "\2" "SSE"      "\3" "AVX"      "\4" "B03"
 
 /*
+ * CPUID Processor extended state Enumeration Fn0000000d
+ *
+ * %ecx == 0: supported features info:
+ *     %edx:%eax bits valid for XCR0
+ *     %ebx Save area size for features enabled in XCR0
+ *     %ecx Maximim save area size for all cpu features
+ *
+ * %ecx == 1: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
+ *
+ * %ecx >= 2: Save area details for XCR0 bit n
+ *     %eax: size of save area for this feature
+ *     %ebx: offset of save area for this feature
+ *     %ecx, %edx: reserved
+ *     All of %eax, %ebx, %ecx and %edx zero for unsupported features.
+ */
+
+#define        CPUID_PES1_XSAVEOPT     0x00000001      /* xsaveopt instruction */
+
+#define CPUID_PES1_FLAGS       "\20" \
+       "\1" "XSAVEOPT"
+
+/*
  * Model-specific registers for the i386 family
  */
 #define MSR_P5_MC_ADDR         0x000   /* P5 only */