[src/trunk]: src/sys/lib/libunwind Add OR1K support

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e1ea567df0e6
branches:  trunk
changeset: 802126:e1ea567df0e6
user:      matt <matt%NetBSD.org@localhost>
date:      Wed Sep 03 19:27:21 2014 +0000

description:
Add OR1K support

diffstat:

 sys/lib/libunwind/Registers.hpp      |  69 ++++++++++++++++++++++++++++++
 sys/lib/libunwind/unwind_registers.S |  81 ++++++++++++++++++++++++++++++++++++
 2 files changed, 150 insertions(+), 0 deletions(-)

diffs (174 lines):

diff -r 0ebb5ef0d851 -r e1ea567df0e6 sys/lib/libunwind/Registers.hpp
--- a/sys/lib/libunwind/Registers.hpp   Wed Sep 03 19:26:31 2014 +0000
+++ b/sys/lib/libunwind/Registers.hpp   Wed Sep 03 19:27:21 2014 +0000
@@ -1024,6 +1024,73 @@
   uint64_t fpreg[32];
 };
 
+enum {
+  DWARF_OR1K_R0 = 0,
+  DWARF_OR1K_SP = 1,
+  DWARF_OR1K_LR = 9,
+  DWARF_OR1K_R31 = 31,
+  DWARF_OR1K_FPCSR = 32,
+
+  REGNO_OR1K_R0 = 0,
+  REGNO_OR1K_SP = 1,
+  REGNO_OR1K_LR = 9,
+  REGNO_OR1K_R31 = 31,
+  REGNO_OR1K_FPCSR = 32,
+};
+
+class Registers_or1k {
+public:
+  enum {
+    LAST_REGISTER = REGNO_OR1K_FPCSR,
+    LAST_RESTORE_REG = REGNO_OR1K_FPCSR,
+    RETURN_OFFSET = 0,
+  };
+
+  __dso_hidden Registers_or1k();
+
+  static int dwarf2regno(int num) {
+    if (num >= DWARF_OR1K_R0 && num <= DWARF_OR1K_R31)
+      return REGNO_OR1K_R0 + (num - DWARF_OR1K_R0);
+    if (num == DWARF_OR1K_FPCSR)
+      return REGNO_OR1K_FPCSR;
+    return LAST_REGISTER + 1;
+  }
+
+  bool validRegister(int num) const {
+    return num >= 0 && num <= LAST_RESTORE_REG;
+  }
+
+  uint64_t getRegister(int num) const {
+    assert(validRegister(num));
+    return reg[num];
+  }
+
+  void setRegister(int num, uint64_t value) {
+    assert(validRegister(num));
+    reg[num] = value;
+  }
+
+  uint64_t getIP() const { return reg[REGNO_OR1K_LR]; }
+
+  void setIP(uint64_t value) { reg[REGNO_OR1K_LR] = value; }
+
+  uint64_t getSP() const { return reg[REGNO_OR1K_SP]; }
+
+  void setSP(uint64_t value) { reg[REGNO_OR1K_SP] = value; }
+
+  bool validFloatVectorRegister(int num) const {
+    return false;
+  }
+
+  void copyFloatVectorRegister(int num, uint64_t addr_) {
+  }
+
+  __dso_hidden void jumpto() const __dead;
+
+private:
+  uint32_t reg[REGNO_OR1K_FPCSR + 1];
+};
+
 #if __i386__
 typedef Registers_x86 NativeUnwindRegisters;
 #elif __x86_64__
@@ -1052,6 +1119,8 @@
 typedef Registers_Alpha NativeUnwindRegisters;
 #elif __hppa__
 typedef Registers_HPPA NativeUnwindRegisters;
+#elif __or1k__
+typedef Registers_or1k NativeUnwindRegisters;
 #endif
 } // namespace _Unwind
 
diff -r 0ebb5ef0d851 -r e1ea567df0e6 sys/lib/libunwind/unwind_registers.S
--- a/sys/lib/libunwind/unwind_registers.S      Wed Sep 03 19:26:31 2014 +0000
+++ b/sys/lib/libunwind/unwind_registers.S      Wed Sep 03 19:27:21 2014 +0000
@@ -1253,3 +1253,84 @@
        bv,n %r0(%r2)
 EXIT(_ZNK7_Unwind14Registers_HPPA6jumptoEv)
 #endif
+
+#ifdef __or1k__
+ENTRY_NP(_ZN7_Unwind14Registers_or1kC1Ev)
+       l.sw    (0*3)(r3), r0
+       l.sw    (1*3)(r3), r1
+       l.sw    (2*3)(r3), r2
+       l.sw    (3*3)(r3), r3
+       l.sw    (4*3)(r3), r4
+       l.sw    (5*3)(r3), r5
+       l.sw    (6*3)(r3), r6
+       l.sw    (7*3)(r3), r7
+       l.sw    (8*3)(r3), r8
+       l.sw    (9*3)(r3), r9
+       l.sw    (10*3)(r3), r10
+       l.sw    (11*3)(r3), r11
+       l.sw    (12*3)(r3), r12
+       l.sw    (13*3)(r3), r13
+       l.sw    (14*3)(r3), r14
+       l.sw    (15*3)(r3), r15
+       l.sw    (16*3)(r3), r16
+       l.sw    (17*3)(r3), r17
+       l.sw    (18*3)(r3), r18
+       l.sw    (19*3)(r3), r19
+       l.sw    (20*3)(r3), r20
+       l.sw    (21*3)(r3), r21
+       l.sw    (22*3)(r3), r22
+       l.sw    (23*3)(r3), r23
+       l.sw    (24*3)(r3), r24
+       l.sw    (25*3)(r3), r25
+       l.sw    (26*3)(r3), r26
+       l.sw    (27*3)(r3), r27
+       l.sw    (28*3)(r3), r28
+       l.sw    (29*3)(r3), r29
+       l.sw    (30*3)(r3), r30
+       l.sw    (31*3)(r3), r31
+       l.mfspr r4, r0, 20
+       l.sw    (32*4)(r3), r4
+       l.jr    lr
+       l.nop
+END(_ZN7_Unwind14Registers_or1kC1Ev)
+
+ENTRY_NP(_ZNK7_Unwind14Registers_or1k6jumptoEv)
+       l.lwz   r6, (32*4)(r3)
+       l.mtspr r0, r6, 20
+       l.lwz   r0, (0*4)(r3)
+       l.lwz   r1, (1*4)(r3)
+       l.lwz   r2, (2*4)(r3)
+       l.lwz   r4, (4*4)(r3)
+       l.lwz   r5, (5*4)(r3)
+       l.lwz   r6, (6*4)(r3)
+       l.lwz   r7, (7*4)(r3)
+       l.lwz   r8, (8*4)(r3)
+       l.lwz   r9, (9*4)(r3)
+       l.lwz   r10, (10*4)(r3)
+       l.lwz   r11, (11*4)(r3)
+       l.lwz   r12, (12*4)(r3)
+       l.lwz   r13, (13*4)(r3)
+       l.lwz   r14, (14*4)(r3)
+       l.lwz   r15, (15*4)(r3)
+       l.lwz   r16, (16*4)(r3)
+       l.lwz   r17, (17*4)(r3)
+       l.lwz   r18, (18*4)(r3)
+       l.lwz   r19, (19*4)(r3)
+       l.lwz   r20, (20*4)(r3)
+       l.lwz   r21, (21*4)(r3)
+       l.lwz   r22, (22*4)(r3)
+       l.lwz   r23, (23*4)(r3)
+       l.lwz   r24, (24*4)(r3)
+       l.lwz   r25, (25*4)(r3)
+       l.lwz   r26, (26*4)(r3)
+       l.lwz   r27, (27*4)(r3)
+       l.lwz   r28, (28*4)(r3)
+       l.lwz   r29, (29*4)(r3)
+       l.lwz   r30, (30*4)(r3)
+       l.lwz   r31, (31*4)(r3)
+
+       l.lwz   r3, (3*4)(r3)           /* return r3 */
+       l.jr    lr
+END(_ZNK7_Unwind14Registers_or1k6jumptoEv)
+
+#endif