[src/trunk]: src/sys/arch/arm/samsung Add PLL registers and PLL conversion ma...

[reinoud <reinoud%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8284d9ad3bc2
branches:  trunk
changeset: 802017:8284d9ad3bc2
user:      reinoud <reinoud%NetBSD.org@localhost>
date:      Thu Aug 28 11:51:02 2014 +0000

description:
Add PLL registers and PLL conversion macros

diffstat:

 sys/arch/arm/samsung/exynos_reg.h |  19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diffs (29 lines):

diff -r 7444e22e7b56 -r 8284d9ad3bc2 sys/arch/arm/samsung/exynos_reg.h
--- a/sys/arch/arm/samsung/exynos_reg.h Thu Aug 28 11:48:22 2014 +0000
+++ b/sys/arch/arm/samsung/exynos_reg.h Thu Aug 28 11:51:02 2014 +0000
@@ -112,6 +112,25 @@
 #define EXYNOS_USB_FREQ                        EXYNOS_F_IN_FREQ/* 24 Mhz */
 
 
+/* PLLs */
+#define PLL_LOCK_OFFSET                        0x000
+#define PLL_CON0_OFFSET                        0x100
+#define PLL_CON1_OFFSET                        0x104
+
+#define PLL_CON0_ENABLE                        __BIT(31)
+#define PLL_CON0_LOCKED                        __BIT(29)       /* has the PLL locked on */
+#define PLL_CON0_M                     __BITS(16,25)   /* PLL M divide value */
+#define PLL_CON0_P                     __BITS( 8,13)   /* PLL P divide value */
+#define PLL_CON0_S                     __BITS( 0, 2)   /* PLL S divide value */
+
+#define PLL_PMS2FREQ(F, M, P, S) (((M)*(F))/((P)*(1<<(S))))
+#define PLL_FREQ(f, v) PLL_PMS2FREQ( \
+       (f),\
+       __SHIFTOUT((v), PLL_CON0_M),\
+       __SHIFTOUT((v), PLL_CON0_P),\
+       __SHIFTOUT((v), PLL_CON0_S))
+
+
 /* Watchdog register definitions */
 #define EXYNOS_WDT_WTCON               0x0000
 #define  WTCON_PRESCALER               __BITS(15,8)