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[src/trunk]: src/sys/arch/arm/nvidia Tegra SATA ungating support



details:   https://anonhg.NetBSD.org/src/rev/5b7c30e599d1
branches:  trunk
changeset: 808249:5b7c30e599d1
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun May 10 15:31:48 2015 +0000

description:
Tegra SATA ungating support

diffstat:

 sys/arch/arm/nvidia/tegra_ahcisata.c |  60 ++++++++++++++++++++++++++++++++++-
 sys/arch/arm/nvidia/tegra_car.c      |  40 ++++++++++++++++++++++-
 sys/arch/arm/nvidia/tegra_carreg.h   |  48 ++++++++++++++++++++++++++++-
 sys/arch/arm/nvidia/tegra_var.h      |   4 +-
 4 files changed, 145 insertions(+), 7 deletions(-)

diffs (284 lines):

diff -r f3cbec688707 -r 5b7c30e599d1 sys/arch/arm/nvidia/tegra_ahcisata.c
--- a/sys/arch/arm/nvidia/tegra_ahcisata.c      Sun May 10 14:08:54 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_ahcisata.c      Sun May 10 15:31:48 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_ahcisata.c,v 1.2 2015/04/26 16:41:04 jmcneill Exp $ */
+/* $NetBSD: tegra_ahcisata.c,v 1.3 2015/05/10 15:31:48 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.2 2015/04/26 16:41:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.3 2015/05/10 15:31:48 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -42,15 +42,22 @@
 #include <dev/ic/ahcisatavar.h>
 
 #include <arm/nvidia/tegra_var.h>
+#include <arm/nvidia/tegra_ahcisatareg.h>
+
+#define TEGRA_AHCISATA_OFFSET  0x7000
 
 static int     tegra_ahcisata_match(device_t, cfdata_t, void *);
 static void    tegra_ahcisata_attach(device_t, device_t, void *);
 
 struct tegra_ahcisata_softc {
        struct ahci_softc       sc;
+       bus_space_tag_t         sc_bst;
+       bus_space_handle_t      sc_bsh;
        void                    *sc_ih;
 };
 
+static void    tegra_ahcisata_init(struct tegra_ahcisata_softc *);
+
 CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc),
        tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL);
 
@@ -67,17 +74,26 @@
        struct tegraio_attach_args * const tio = aux;
        const struct tegra_locators * const loc = &tio->tio_loc;
 
+       sc->sc_bst = tio->tio_bst;
+       bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+           loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
        sc->sc.sc_atac.atac_dev = self;
        sc->sc.sc_dmat = tio->tio_dmat;
        sc->sc.sc_ahcit = tio->tio_bst;
        sc->sc.sc_ahcis = loc->loc_size;
        bus_space_subregion(tio->tio_bst, tio->tio_bsh,
-           loc->loc_offset, loc->loc_size, &sc->sc.sc_ahcih);
+           loc->loc_offset + TEGRA_AHCISATA_OFFSET,
+           loc->loc_size - TEGRA_AHCISATA_OFFSET, &sc->sc.sc_ahcih);
        sc->sc.sc_ahci_ports = 1;
 
        aprint_naive("\n");
        aprint_normal(": SATA\n");
 
+       tegra_car_periph_sata_enable();
+
+       tegra_ahcisata_init(sc);
+
        sc->sc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
            ahci_intr, &sc->sc);
        if (sc->sc_ih == NULL) {
@@ -89,3 +105,41 @@
 
        ahci_attach(&sc->sc);
 }
+
+static void
+tegra_ahcisata_init(struct tegra_ahcisata_softc *sc)
+{
+       bus_space_tag_t bst = sc->sc_bst;
+       bus_space_handle_t bsh = sc->sc_bsh;
+
+       /* Enable IFPS device block */
+       tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG,
+           TEGRA_SATA_CONFIGURATION_EN_FPCI, 0);
+
+       /* Backdoor update the programming interface field and class code */
+       tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
+           TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN, 0);
+       bus_space_write_4(bst, bsh, TEGRA_T_SATA0_BKDOOR_CC_REG,
+           __SHIFTIN(0x1016, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) |
+           __SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF));
+       tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
+           0, TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN);
+
+       /* Enable access and bus mastering */
+       tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG,
+           TEGRA_T_SATA0_CFG1_SERR |
+           TEGRA_T_SATA0_CFG1_BUS_MASTER |
+           TEGRA_T_SATA0_CFG1_MEM_SPACE |
+           TEGRA_T_SATA0_CFG1_IO_SPACE,
+           0);
+
+       /* MMIO setup */
+       bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG,
+           __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START));
+       bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG,
+           __SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS));
+
+       /* Enable interrupts */
+       tegra_reg_set_clear(bst, bsh, TEGRA_SATA_INTR_MASK_REG,
+           TEGRA_SATA_INTR_MASK_IP_INT, 0);
+}
diff -r f3cbec688707 -r 5b7c30e599d1 sys/arch/arm/nvidia/tegra_car.c
--- a/sys/arch/arm/nvidia/tegra_car.c   Sun May 10 14:08:54 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_car.c   Sun May 10 15:31:48 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_car.c,v 1.7 2015/05/10 11:04:59 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.8 2015/05/10 15:31:48 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.7 2015/05/10 11:04:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.8 2015/05/10 15:31:48 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -40,6 +40,7 @@
 
 #include <arm/nvidia/tegra_reg.h>
 #include <arm/nvidia/tegra_carreg.h>
+#include <arm/nvidia/tegra_pmcreg.h>
 #include <arm/nvidia/tegra_var.h>
 
 static int     tegra_car_match(device_t, cfdata_t, void *);
@@ -80,8 +81,10 @@
        aprint_naive("\n");
        aprint_normal(": CAR\n");
 
+       printf("CAR_PLLE_BASE_REG = %#x\n", bus_space_read_4(sc->sc_bst, sc->sc_bsh, CAR_PLLE_BASE_REG));
        aprint_verbose_dev(self, "PLLX = %u Hz\n", tegra_car_pllx_rate());
        aprint_verbose_dev(self, "PLLC = %u Hz\n", tegra_car_pllc_rate());
+       aprint_verbose_dev(self, "PLLE = %u Hz\n", tegra_car_plle_rate());
        aprint_verbose_dev(self, "PLLU = %u Hz\n", tegra_car_pllu_rate());
        aprint_verbose_dev(self, "PLLP0 = %u Hz\n", tegra_car_pllp0_rate());
 }
@@ -141,6 +144,13 @@
 }
 
 u_int
+tegra_car_plle_rate(void)
+{
+       return tegra_car_pll_rate(CAR_PLLE_BASE_REG, CAR_PLLE_BASE_DIVM,
+           CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML);
+}
+
+u_int
 tegra_car_pllu_rate(void)
 {
        bus_space_tag_t bst;
@@ -401,3 +411,29 @@
        bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG,
            CAR_DEV_W_HDA2HDMICODEC);
 }
+
+void
+tegra_car_periph_sata_enable(void)
+{
+       bus_space_tag_t bst;
+       bus_space_handle_t bsh;
+
+       tegra_car_get_bs(&bst, &bsh);
+
+       /* Enable CML clock for SATA */
+       tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG,
+           CAR_PLLE_AUX_CML1_OEN, 0);
+
+       /* De-assert reset to SATA PADPLL */
+       tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
+           0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE);
+       delay(15);
+
+       /* Ungate SAX partition in the PMC */
+       tegra_pmc_power(PMC_PARTID_SAX, true);
+
+       /* Turn on the clocks to SATA and de-assert resets */
+       bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_SATA);
+       bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_SATACOLD);
+       bus_space_write_4(bst, bsh, CAR_RST_DEV_V_CLR_REG, CAR_DEV_V_SATA);
+}
diff -r f3cbec688707 -r 5b7c30e599d1 sys/arch/arm/nvidia/tegra_carreg.h
--- a/sys/arch/arm/nvidia/tegra_carreg.h        Sun May 10 14:08:54 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_carreg.h        Sun May 10 15:31:48 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_carreg.h,v 1.9 2015/05/10 11:12:07 jmcneill Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.10 2015/05/10 15:31:48 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -89,6 +89,17 @@
 
 #define CAR_PLLX_MISC_REG      0xe4
 
+#define CAR_PLLE_BASE_REG      0xe8
+#define CAR_PLLE_BASE_ENABLE           __BIT(30)
+#define CAR_PLLE_BASE_LOCK_OVERRIDE    __BIT(29)
+#define CAR_PLLE_BASE_FDIV48           __BIT(28)
+#define CAR_PLLE_BASE_DIVP_CML         __BITS(27,24)
+#define CAR_PLLE_BASE_EXT_SETUP_23_16  __BITS(23,16)
+#define CAR_PLLE_BASE_DIVN             __BITS(15,8)
+#define CAR_PLLE_BASE_DIVM             __BITS(7,0)
+
+#define CAR_PLLE_MISC_REG      0xec
+
 #define CAR_CLKSRC_UARTA_REG           0x178
 #define CAR_CLKSRC_UARTB_REG           0x17c
 #define CAR_CLKSRC_UARTC_REG           0x1a0
@@ -270,4 +281,39 @@
 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP   __BIT(1)
 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN __BIT(0)
 
+#define CAR_PLLE_AUX_REG               0x48c
+#define CAR_PLLE_AUX_SS_SEQ_INCLUDE            __BIT(31)
+#define CAR_PLLE_AUX_REF_SEL_PLLREFE           __BIT(28)
+#define CAR_PLLE_AUX_SEQ_STATE                 __BITS(27,26)
+#define CAR_PLLE_AUX_SEQ_START_STATE           __BIT(25)
+#define CAR_PLLE_AUX_SEQ_ENABLE                        __BIT(24)
+#define CAR_PLLE_AUX_SS_DLY                    __BITS(23,16)
+#define CAR_PLLE_AUX_LOCK_DLY                  __BITS(15,8)
+#define CAR_PLLE_AUX_FAST_PT                   __BIT(7)
+#define CAR_PLLE_AUX_SS_SWCTL                  __BIT(6)
+#define CAR_PLLE_AUX_CONFIG_SWCTL              __BIT(5)
+#define CAR_PLLE_AUX_ENABLE_SWCTL              __BIT(4)
+#define CAR_PLLE_AUX_USE_LOCKDET               __BIT(3)
+#define CAR_PLLE_AUX_REF_SRC                   __BIT(2)
+#define CAR_PLLE_AUX_CML1_OEN                  __BIT(1)
+#define CAR_PLLE_AUX_CML0_OEN                  __BIT(0)
+
+#define CAR_SATA_PLL_CFG0_REG          0x490
+#define CAR_SATA_PLL_CFG0_SEQ_STATE            __BITS(27,26)
+#define CAR_SATA_PLL_CFG0_SEQ_START_STATE      __BIT(25)
+#define CAR_SATA_PLL_CFG0_SEQ_ENABLE           __BIT(24)
+#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
+#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
+#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE        __BIT(5)
+#define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL         __BIT(4)
+#define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET   __BIT(2)
+#define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
+#define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL   __BIT(0)
+
+#define CAR_SATA_PLL_CFG1_REG          0x494
+#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24)
+#define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16)
+#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY   __BITS(15,8)
+#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)
+
 #endif /* _ARM_TEGRA_CARREG_H */
diff -r f3cbec688707 -r 5b7c30e599d1 sys/arch/arm/nvidia/tegra_var.h
--- a/sys/arch/arm/nvidia/tegra_var.h   Sun May 10 14:08:54 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_var.h   Sun May 10 15:31:48 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_var.h,v 1.12 2015/05/10 11:04:59 jmcneill Exp $ */
+/* $NetBSD: tegra_var.h,v 1.13 2015/05/10 15:31:48 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -75,6 +75,7 @@
 
 u_int  tegra_car_osc_rate(void);
 u_int  tegra_car_pllc_rate(void);
+u_int  tegra_car_plle_rate(void);
 u_int  tegra_car_pllx_rate(void);
 u_int  tegra_car_pllu_rate(void);
 u_int  tegra_car_pllp0_rate(void);
@@ -83,6 +84,7 @@
 int    tegra_car_periph_sdmmc_set_div(u_int, u_int);
 int    tegra_car_periph_usb_enable(u_int);
 void   tegra_car_periph_hda_enable(void);
+void   tegra_car_periph_sata_enable(void);
 void   tegra_car_utmip_init(void);
 void   tegra_car_utmip_enable(u_int);
 



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