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[src/netbsd-8]: src Pull up following revision(s) (requested by tsutsui in ti...
details: https://anonhg.NetBSD.org/src/rev/b237822de852
branches: netbsd-8
changeset: 851466:b237822de852
user: martin <martin%NetBSD.org@localhost>
date: Tue Mar 13 13:41:13 2018 +0000
description:
Pull up following revision(s) (requested by tsutsui in ticket #624):
sys/arch/atari/stand/xxboot/sdboot/milan/Makefile: revision 1.4
sys/arch/atari/dev/nvram.c: revision 1.21
sys/arch/atari/conf/MILAN.in: revision 1.28
sys/arch/atari/atari/pmap_bootstrap.c: revision 1.9
sys/dev/isa/fd.c: revision 1.111
sys/arch/atari/atari/bus.c: revision 1.60
sys/arch/atari/stand/xxboot/ahdi-xxboot/milan/Makefile: revision 1.4
sys/arch/atari/atari/locore.s: revision 1.111
sys/arch/atari/isa/isa_machdep.c: revision 1.41
distrib/sets/lists/base/md.atari: revision 1.55
sys/arch/atari/pci/pci_machdep.c: revision 1.55
sys/arch/atari/pci/pci_machdep.c: revision 1.56
sys/arch/atari/include/vmparam.h: revision 1.32
sys/arch/atari/isa/isa_milan.c: revision 1.15
sys/arch/atari/isa/isa_milan.c: revision 1.16
sys/arch/atari/atari/bus.c: revision 1.59
sys/arch/atari/atari/atari_init.c: revision 1.101
sys/arch/atari/pci/pci_milan.c: revision 1.15
Fix I/O access failures for regions allocated by bus_space_map(9) on Milan.
Passing to PMAP_WIRED against I/O spaces seems problematic,
probably after yamt-km branch merge, which was committed
between NetBSD 3.0 and NetBSD 4.0.
(i.e. ISA and PCI devices on Milan didn't work after 4.0 release)
XXX:
According to pmap(9) man page, the "flags" arg for pmap_enter(9)
doesn't take VM_PROT_READ and VM_PROT_WRITE, but pmap_enter()
implementation in sys/arch/m68k/m68k/pmap_motolora.c historically
checks them.
Fix silent hang during config_console() (before consinit()) on Milan.
config_console() was a dirty hack used by ancient m68k ports
to probe and initialize console devices before "real" configure(9),
using subset of configure(9) functions.
In that case, most device specific data (except I/O access method)
are not initialized so we must not access device specific device_t and
softc structures in config_console() cases.
Fix silent hang after isa_intr_establish() on Milan.
The problems (wrong macro replacements) were slipped in rev 1.107:
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/atari/atari/locore.s#rev1.107
Handle yet another atari specific quirk in the MI ISA fdc(4)/fd(4) driver.
This makes fd(4) drive(s) (which is necessary for installation)
properly attached on Milan.
atari uses "fdcisa" and "fdisa" for ISA fdc to co-exist other fd(4)
drivers, on-board (atari/dev/fd.c) one and Hades (atari/dev/hdfd.c) one.
Use a proper PSL value to be passed to splx(9) functions.
This should have been changed on yamt-splraiseipl branch merge
back in 2006, which made MI IPL_xxx values independent from
m68k MD PSL values for the %sr register.
Restore piixide(4) for Milan and disable other pciide devices.
piixide was removed in rev 1.18 and the log message said
"because Intel IDE disk controllers only exist as part of
Intel chipsets for x86 systems" but the Milan actually has
the Intel 82371FB southbridge on its board.
Other pciide devices are unlikely necessary for the default
kernel for such a rare machine.
Also fix pasto in comment.
Skip NVRAM checksum check and re-initialization on Milan.
Milan's firmware seems to use different check method.
Ack EOI for IRQ_SLAVE of the master PIC after ack for IRQ of the slave PIC.
I'm not sure if there are possible races in the original code, but
this is what i8259_asm_ack2() in sys/arch/x86/include/i8259.h does
and it looks this change makes a Milan kernel a bit stable.
Replace CRTC register values with ones taken from sys/dev/ic/vga_subr.c.
This fixes noise around column 3 and 4 and makes screen output clearer
on Milan with S3 Trio64V.
Explicitly setup the secondary IDE interrupt of PIIX on Milan.
The secondary IDE interrupt is connected to MBIRQ0 on PIIX, but
the Milan's ROM bootloader (at least version 0.99.7) doesn't seem
to setup the MBIRQ0 register to route it to IRQ15.
On Milan, also explicitly disable MBIRQ1 on PIIX.
Milan's ROM bootloader v1.2 and v1.4 incorrectly set MBIRQ0 connected
to the secondary IDE to IRQ14 (not 15) and unused MBIRQ1 to IRQ15,
so both IDE channels don't work properly.
Add dumb memory probe routines for Milan to use all available memory.
Tested on Milan with 32Mx1, 32Mx4, 128MBx1, and 128MBx3.
(bootloader ROM fails to load TOS with 128MBx4)
No particular comment on port-atari@:
http://mail-index.netbsd.org/port-atari/2018/02/09/msg000580.html
Provide wdboot as a copy of sdboot for Milan.
It looks Milan's bootloader ROM emulates IDE disks as SCSI disks
so sdboot works for them, but atari's installboot checks a specified
device name and requires wdboot for wd(4) devices.
Fix another possible out of bounds.
Replace bus_dmamap_sync(9) op with a newer one taken from m68k/bus_dma.c.
This could fix memory corruption issue caused by PREREAD ops with regions
whose boundaries are not aligned at cacheline size.
diffstat:
distrib/sets/lists/base/md.atari | 4 +-
sys/arch/atari/atari/atari_init.c | 245 ++++++++++++++++-
sys/arch/atari/atari/bus.c | 213 ++++++++++++-
sys/arch/atari/atari/locore.s | 6 +-
sys/arch/atari/atari/pmap_bootstrap.c | 12 +-
sys/arch/atari/conf/MILAN.in | 31 +-
sys/arch/atari/dev/nvram.c | 18 +-
sys/arch/atari/include/vmparam.h | 6 +-
sys/arch/atari/isa/isa_machdep.c | 13 +-
sys/arch/atari/isa/isa_milan.c | 22 +-
sys/arch/atari/pci/pci_machdep.c | 23 +-
sys/arch/atari/pci/pci_milan.c | 40 ++-
sys/arch/atari/stand/xxboot/ahdi-xxboot/milan/Makefile | 3 +-
sys/arch/atari/stand/xxboot/sdboot/milan/Makefile | 3 +-
sys/dev/isa/fd.c | 8 +-
15 files changed, 537 insertions(+), 110 deletions(-)
diffs (truncated from 1069 to 300 lines):
diff -r c9f4c6999704 -r b237822de852 distrib/sets/lists/base/md.atari
--- a/distrib/sets/lists/base/md.atari Tue Mar 13 13:29:57 2018 +0000
+++ b/distrib/sets/lists/base/md.atari Tue Mar 13 13:41:13 2018 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: md.atari,v 1.54 2014/08/06 12:15:01 martin Exp $
+# $NetBSD: md.atari,v 1.54.16.1 2018/03/13 13:41:14 martin Exp $
./sbin/ahdilabel base-sysutil-root
./sbin/binpatch base-sysutil-root
./sbin/edahdi base-sysutil-root
@@ -10,6 +10,8 @@
./usr/mdec/milan/fdboot base-sysutil-bin
./usr/mdec/milan/sdb00t.ahdi base-sysutil-bin
./usr/mdec/milan/sdboot base-sysutil-bin
+./usr/mdec/milan/wdb00t.ahdi base-sysutil-bin
+./usr/mdec/milan/wdboot base-sysutil-bin
./usr/mdec/milan/xxboot.ahdi base-sysutil-bin
./usr/mdec/std base-sysutil-bin
./usr/mdec/std/boot.atari base-sysutil-bin
diff -r c9f4c6999704 -r b237822de852 sys/arch/atari/atari/atari_init.c
--- a/sys/arch/atari/atari/atari_init.c Tue Mar 13 13:29:57 2018 +0000
+++ b/sys/arch/atari/atari/atari_init.c Tue Mar 13 13:41:13 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: atari_init.c,v 1.100 2012/08/10 17:43:32 tsutsui Exp $ */
+/* $NetBSD: atari_init.c,v 1.100.32.1 2018/03/13 13:41:13 martin Exp $ */
/*
* Copyright (c) 1995 Leo Weppelman
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: atari_init.c,v 1.100 2012/08/10 17:43:32 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: atari_init.c,v 1.100.32.1 2018/03/13 13:41:13 martin Exp $");
#include "opt_ddb.h"
#include "opt_mbtype.h"
@@ -91,9 +91,26 @@
static void mmu040_setup(paddr_t, u_int, paddr_t, psize_t, paddr_t, paddr_t);
#endif
+#if defined(_MILANHW_)
+static u_int milan_probe_bank_1(paddr_t paddr);
+static u_int milan_probe_bank(paddr_t paddr);
+
+#define NBANK 2
+#define NSLOT 4
+
+#define MB(n) ((n) * 1024 * 1024)
+#define MB_END(n) (MB(n) - 1)
+#define MAGIC_4M (4 - 1)
+#define MAGIC_4M_INV ((uint8_t)~MAGIC_4M)
+#define MAGIC_8M (8 - 1)
+#define MAGIC_16M (16 - 1)
+#define MAGIC_32M (32 - 1)
+#define MAGIC_64M (64 - 1)
+#endif
+
/*
* Extent maps to manage all memory space, including I/O ranges. Allocate
- * storage for 8 regions in each, initially. Later, iomem_malloc_safe
+ * storage for 16 regions in each, initially. Later, iomem_malloc_safe
* will indicate that it's safe to use malloc() to dynamically allocate
* region descriptors.
* This means that the fixed static storage is only used for registrating
@@ -102,7 +119,7 @@
* The extent maps are not static! They are used for bus address space
* allocation.
*/
-static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
+static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)];
struct extent *iomem_ex;
int iomem_malloc_safe;
@@ -204,23 +221,67 @@
paddr_t kbase;
u_int kstsize;
paddr_t Sysptmap_pa;
-
#if defined(_MILANHW_)
- /* XXX
- * XXX The right place todo this is probably the booter (Leo)
- * XXX More than 16MB memory is not yet supported on the Milan!
+ /*
* The Milan Lies about the presence of TT-RAM. If you insert
* 16MB it is split in 14MB ST starting at address 0 and 2MB TT RAM,
- * starting at address 16MB.
+ * starting at address 16MB as the BIOS remapping memory using MMU.
+ *
+ * Milan actually has four SIMM slots and each slot has two banks,
+ * so it could have up to 8 memory segment regions.
*/
- stphysize += ttphysize;
- ttphysize = ttphystart = 0;
-#endif
+ const paddr_t simm_base[NBANK][NSLOT] = {
+ /* slot 0-3, bank 0 */
+ { 0x00000000, 0x04000000, 0x08000000, 0x0c000000 },
+ /* slot 0-3, bank 1 */
+ { 0x10000000, 0x14000000, 0x18000000, 0x1c000000 }
+ };
+ int slot, bank, seg;
+ u_int mb;
+
+ /* On Milan, all RAMs are fast 32 bit so no need to reloc kernel */
+ reloc_kernel = 0;
+
+ /* probe memory region in all SIMM slots and banks */
+ seg = 0;
+ ttphysize = 0;
+ for (bank = 0; bank < 2; bank++) {
+ for (slot = 0; slot < 4; slot++) {
+ if (bank == 0 && slot == 0) {
+ /*
+ * The first bank has at least 16MB because
+ * the Milan's ROM bootloader requires it
+ * to allocate ST RAM.
+ */
+ mb = milan_probe_bank_1(simm_base[bank][slot]);
+ boot_segs[0].start = 0;
+ boot_segs[0].end = MB(mb);
+ stphysize = MB(mb);
+ seg++;
+ } else {
+ /*
+ * The rest banks could be empty or
+ * have 4, 8, 16, 32, or 64MB.
+ */
+ mb = milan_probe_bank(simm_base[bank][slot]);
+ if (mb > 0) {
+ boot_segs[seg].start =
+ simm_base[bank][slot];
+ boot_segs[seg].end =
+ simm_base[bank][slot] + MB(mb);
+ ttphysize += MB(mb);
+ seg++;
+ }
+ }
+ }
+ }
+#else /* _MILANHW_ */
boot_segs[0].start = 0;
boot_segs[0].end = stphysize;
boot_segs[1].start = ttphystart;
boot_segs[1].end = ttphystart + ttphysize;
boot_segs[2].start = boot_segs[2].end = 0; /* End of segments! */
+#endif
/*
* The following is a hack. We do not know how much ST memory we
@@ -484,10 +545,21 @@
usable_segs[0].start = 0;
usable_segs[0].end = stphysize;
usable_segs[0].free_list = VM_FREELIST_STRAM;
+#if defined(_MILANHW_)
+ for (i = 1; i < seg; i++) {
+ usable_segs[i].start = boot_segs[i].start;
+ usable_segs[i].end = boot_segs[i].end;
+ usable_segs[i].free_list = VM_FREELIST_TTRAM;
+ }
+ for (; i < NMEM_SEGS; i++) {
+ usable_segs[i].start = usable_segs[i].end = 0;
+ }
+#else
usable_segs[1].start = ttphystart;
usable_segs[1].end = ttphystart + ttphysize;
usable_segs[1].free_list = VM_FREELIST_TTRAM;
usable_segs[2].start = usable_segs[2].end = 0; /* End of segments! */
+#endif
if (kbase) {
/*
@@ -506,7 +578,7 @@
* available physical memory.
*/
usable_segs[0].first_page = 0;
- for (i = 1; usable_segs[i].start; i++) {
+ for (i = 1; i < NMEM_SEGS && usable_segs[i].start; i++) {
usable_segs[i].first_page = usable_segs[i-1].first_page;
usable_segs[i].first_page +=
(usable_segs[i-1].end - usable_segs[i-1].start) / PAGE_SIZE;
@@ -609,7 +681,7 @@
/*
* Allocate the physical RAM from the extent map
*/
- for (i = 0; boot_segs[i].end != 0; i++) {
+ for (i = 0; i < NMEM_SEGS && boot_segs[i].end != 0; i++) {
if (extent_alloc_region(iomem_ex, boot_segs[i].start,
boot_segs[i].end - boot_segs[i].start, EX_NOWAIT)) {
/* XXX: Ahum, should not happen ;-) */
@@ -624,6 +696,151 @@
intr_init();
}
+#if defined(_MILANHW_)
+/*
+ * Probe and return available memory size in MB at specfied address.
+ * The first slot SIMM have at least 16MB, so check if it has 32 or 64 MB.
+ *
+ * Note it seems Milan does not generate bus errors on accesses against
+ * address regions where memory doesn't exist, but it returns memory images
+ * of lower address of the bank.
+ */
+static u_int
+milan_probe_bank_1(paddr_t start_paddr)
+{
+ volatile uint8_t *base;
+ u_int mb;
+ uint8_t save_16, save_32, save_64;
+
+ /* Assume that this bank has at least 16MB */
+ mb = 16;
+
+ base = (uint8_t *)start_paddr;
+
+ /* save and write a MAGIC at the end of 16MB region */
+ save_16 = base[MB_END(16)];
+ base[MB_END(16)] = MAGIC_16M;
+
+ /* check bus error at the end of 32MB region */
+ if (badbaddr(__UNVOLATILE(base + MB_END(32)), sizeof(uint8_t))) {
+ /* bus error; assume no memory there */
+ goto out16;
+ }
+
+ /* check if the 32MB region is not image of the prior 16MB region */
+ save_32 = base[MB_END(32)];
+ base[MB_END(32)] = MAGIC_32M;
+ if (base[MB_END(32)] != MAGIC_32M || base[MB_END(16)] != MAGIC_16M) {
+ /* no memory or image at the 32MB region */
+ goto out16;
+ }
+ /* we have at least 32MB */
+ mb = 32;
+
+ /* check bus error at the end of 64MB region */
+ if (badbaddr(__UNVOLATILE(base + MB_END(64)), sizeof(uint8_t))) {
+ /* bus error; assume no memory there */
+ goto out32;
+ }
+
+ /* check if the 64MB region is not image of the prior 32MB region */
+ save_64 = base[MB_END(64)];
+ base[MB_END(64)] = MAGIC_64M;
+ if (base[MB_END(64)] != MAGIC_64M || base[MB_END(32)] != MAGIC_32M) {
+ /* no memory or image at the 64MB region */
+ goto out32;
+ }
+ /* we have 64MB */
+ mb = 64;
+ base[MB_END(64)] = save_64;
+ out32:
+ base[MB_END(32)] = save_32;
+ out16:
+ base[MB_END(16)] = save_16;
+
+ return mb;
+}
+
+/*
+ * Probe and return available memory size in MB at specfied address.
+ * The rest slot could be empty so check all possible size.
+ */
+static u_int
+milan_probe_bank(paddr_t start_paddr)
+{
+ volatile uint8_t *base;
+ u_int mb;
+ uint8_t save_4, save_8, save_16;
+
+ /* The rest banks might have no memory */
+ mb = 0;
+
+ base = (uint8_t *)start_paddr;
+
+ /* check bus error at the end of 4MB region */
+ if (badbaddr(__UNVOLATILE(base + MB_END(4)), sizeof(uint8_t))) {
+ /* bus error; assume no memory there */
+ goto out;
+ }
+
+ /* check if the 4MB region has memory */
+ save_4 = base[MB_END(4)];
+ base[MB_END(4)] = MAGIC_4M_INV;
+ if (base[MB_END(4)] != MAGIC_4M_INV) {
+ /* no memory */
+ goto out;
+ }
+ base[MB_END(4)] = MAGIC_4M;
+ if (base[MB_END(4)] != MAGIC_4M) {
+ /* no memory */
+ goto out;
+ }
+ /* we have at least 4MB */
+ mb = 4;
+
+ /* check bus error at the end of 8MB region */
+ if (badbaddr(__UNVOLATILE(base + MB_END(8)), sizeof(uint8_t))) {
+ /* bus error; assume no memory there */
+ goto out4;
+ }
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