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[src/trunk]: src/sys/arch More PCIe / XUSBPAD initialization goo for Tegra210.
details: https://anonhg.NetBSD.org/src/rev/3487f961bfcb
branches: trunk
changeset: 826742:3487f961bfcb
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Tue Sep 26 16:12:45 2017 +0000
description:
More PCIe / XUSBPAD initialization goo for Tegra210.
diffstat:
sys/arch/arm/nvidia/files.tegra | 7 +-
sys/arch/arm/nvidia/tegra210_car.c | 13 ++-
sys/arch/arm/nvidia/tegra210_xusbpad.c | 90 ++++++++++++++++++++++-
sys/arch/arm/nvidia/tegra_pcie.c | 126 +++++++++++++++++++++++++++++++-
sys/arch/arm/nvidia/tegra_pciereg.h | 25 ++++++-
sys/arch/arm/nvidia/tegra_xusb.c | 14 ++-
sys/arch/evbarm/conf/TEGRA | 3 +-
7 files changed, 258 insertions(+), 20 deletions(-)
diffs (truncated from 523 to 300 lines):
diff -r 9ad496d1e49b -r 3487f961bfcb sys/arch/arm/nvidia/files.tegra
--- a/sys/arch/arm/nvidia/files.tegra Tue Sep 26 16:01:58 2017 +0000
+++ b/sys/arch/arm/nvidia/files.tegra Tue Sep 26 16:12:45 2017 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.44 2017/09/22 14:36:22 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.45 2017/09/26 16:12:45 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -88,10 +88,13 @@
file arch/arm/nvidia/tegra124_xusbpad.c tegra124_xusbpad
# XUSB PADCTL (Tegra210)
-device tegra210xpad: tegra_xusbpad
+device tegra210xpad { }: tegra_xusbpad
+device tegra210xphy: tegra210xpad
attach tegra210xpad at fdt with tegra210_xusbpad
+attach tegra210xphy at tegra210xpad
file arch/arm/nvidia/tegra210_xusbpad.c tegra210_xusbpad
+
# UART
attach com at fdt with tegra_com
file arch/arm/nvidia/tegra_com.c tegra_com needs-flag
diff -r 9ad496d1e49b -r 3487f961bfcb sys/arch/arm/nvidia/tegra210_car.c
--- a/sys/arch/arm/nvidia/tegra210_car.c Tue Sep 26 16:01:58 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_car.c Tue Sep 26 16:12:45 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_car.c,v 1.13 2017/09/25 08:55:07 jmcneill Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.14 2017/09/26 16:12:45 jmcneill Exp $ */
/*-
* Copyright (c) 2015-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.13 2017/09/25 08:55:07 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.14 2017/09/26 16:12:45 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -609,6 +609,9 @@
{ "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 },
{ "PLL_U_OUT1", NULL, 48000000, 1 },
{ "PLL_U_OUT2", NULL, 60000000, 1 },
+ { "CML0", NULL, 0, 1 },
+ { "AFI", NULL, 0, 1 },
+ { "PCIE", NULL, 0, 1 },
};
struct tegra210_car_rst {
@@ -817,9 +820,15 @@
tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT);
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_AFI);
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_PCIE);
+
bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD);
bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2);
bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB);
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_AFI);
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIE);
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_PCIEXCLK);
bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY);
bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY);
diff -r 9ad496d1e49b -r 3487f961bfcb sys/arch/arm/nvidia/tegra210_xusbpad.c
--- a/sys/arch/arm/nvidia/tegra210_xusbpad.c Tue Sep 26 16:01:58 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_xusbpad.c Tue Sep 26 16:12:45 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_xusbpad.c,v 1.7 2017/09/25 00:03:34 jmcneill Exp $ */
+/* $NetBSD: tegra210_xusbpad.c,v 1.8 2017/09/26 16:12:45 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.7 2017/09/25 00:03:34 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.8 2017/09/26 16:12:45 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -158,6 +158,17 @@
bool sc_enabled;
};
+struct tegra210_xusbpad_phy_softc {
+ device_t sc_dev;
+ int sc_phandle;
+ struct tegra210_xusbpad_softc *sc_xusbpad;
+};
+
+struct tegra210_xusbpad_phy_attach_args {
+ struct tegra210_xusbpad_softc *paa_xusbpad;
+ int paa_phandle;
+};
+
#define RD4(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
#define WR4(sc, reg, val) \
@@ -550,16 +561,18 @@
}
}
- /* Configure lanes */
+ /* Attach PHYs */
phandle = of_find_firstchild_byname(phandle, "lanes");
if (phandle == -1) {
aprint_error_dev(sc->sc_dev, "no 'pads/%s/lanes' node\n", name);
return;
}
for (child = OF_child(phandle); child; child = OF_peer(child)) {
- if (!fdtbus_status_okay(child))
- continue;
- tegra210_xusbpad_configure_lane(sc, child);
+ struct tegra210_xusbpad_phy_attach_args paa = {
+ .paa_xusbpad = sc,
+ .paa_phandle = child
+ };
+ config_found(sc->sc_dev, &paa, NULL);
}
}
@@ -813,5 +826,70 @@
tegra210_xusbpad_configure_ports(sc);
}
+static void *
+tegra210_xusbpad_phy_acquire(device_t dev, const void *data, size_t len)
+{
+ struct tegra210_xusbpad_phy_softc * const sc = device_private(dev);
+
+ if (len != 0)
+ return NULL;
+
+ return sc;
+}
+
+static void
+tegra210_xusbpad_phy_release(device_t dev, void *priv)
+{
+};
+
+static int
+tegra210_xusbpad_phy_enable(device_t dev, void *priv, bool enable)
+{
+ struct tegra210_xusbpad_phy_softc * const sc = device_private(dev);
+
+ if (enable == false)
+ return ENXIO; /* not implemented */
+
+ tegra210_xusbpad_configure_lane(sc->sc_xusbpad, sc->sc_phandle);
+
+ return 0;
+}
+
+static const struct fdtbus_phy_controller_func tegra210_xusbpad_phy_funcs = {
+ .acquire = tegra210_xusbpad_phy_acquire,
+ .release = tegra210_xusbpad_phy_release,
+ .enable = tegra210_xusbpad_phy_enable,
+};
+
CFATTACH_DECL_NEW(tegra210_xusbpad, sizeof(struct tegra210_xusbpad_softc),
tegra210_xusbpad_match, tegra210_xusbpad_attach, NULL, NULL);
+
+static int
+tegra210_xusbpad_phy_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct tegra210_xusbpad_phy_attach_args * const paa = aux;
+
+ if (!fdtbus_status_okay(paa->paa_phandle))
+ return 0;
+
+ return 1;
+}
+
+static void
+tegra210_xusbpad_phy_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra210_xusbpad_phy_softc * const sc = device_private(self);
+ struct tegra210_xusbpad_phy_attach_args * const paa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = paa->paa_phandle;
+ sc->sc_xusbpad = paa->paa_xusbpad;
+
+ aprint_naive("\n");
+ aprint_normal(": %s\n", fdtbus_get_string(sc->sc_phandle, "name"));
+
+ fdtbus_register_phy_controller(self, sc->sc_phandle, &tegra210_xusbpad_phy_funcs);
+}
+
+CFATTACH_DECL_NEW(tegra210xphy, sizeof(struct tegra210_xusbpad_phy_softc),
+ tegra210_xusbpad_phy_match, tegra210_xusbpad_phy_attach, NULL, NULL);
diff -r 9ad496d1e49b -r 3487f961bfcb sys/arch/arm/nvidia/tegra_pcie.c
--- a/sys/arch/arm/nvidia/tegra_pcie.c Tue Sep 26 16:01:58 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra_pcie.c Tue Sep 26 16:12:45 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_pcie.c,v 1.20 2017/09/25 08:55:27 jmcneill Exp $ */
+/* $NetBSD: tegra_pcie.c,v 1.21 2017/09/26 16:12:45 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.20 2017/09/25 08:55:27 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.21 2017/09/26 16:12:45 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -48,6 +48,7 @@
#include <arm/nvidia/tegra_reg.h>
#include <arm/nvidia/tegra_pciereg.h>
+#include <arm/nvidia/tegra_pmcreg.h>
#include <arm/nvidia/tegra_var.h>
#include <dev/fdt/fdtvar.h>
@@ -74,6 +75,7 @@
bus_dma_tag_t sc_dmat;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh_afi;
+ bus_space_handle_t sc_bsh_pads;
bus_space_handle_t sc_bsh_rpconf;
int sc_phandle;
@@ -92,6 +94,7 @@
static int tegra_pcie_intr(void *);
static void tegra_pcie_init(pci_chipset_tag_t, void *);
static void tegra_pcie_enable(struct tegra_pcie_softc *);
+static void tegra_pcie_enable_ports(struct tegra_pcie_softc *);
static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *);
static void tegra_pcie_setup(struct tegra_pcie_softc * const);
static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const,
@@ -143,15 +146,19 @@
struct fdt_attach_args * const faa = aux;
struct extent *ioext, *memext, *pmemext;
struct pcibus_attach_args pba;
- bus_addr_t afi_addr, cs_addr;
- bus_size_t afi_size, cs_size;
+ bus_addr_t afi_addr, cs_addr, pads_addr;
+ bus_size_t afi_size, cs_size, pads_size;
char intrstr[128];
int error;
- if (fdtbus_get_reg(faa->faa_phandle, 1, &afi_addr, &afi_size) != 0) {
+ if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) {
aprint_error(": couldn't get afi registers\n");
return;
}
+ if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) {
+ aprint_error(": couldn't get pads registers\n");
+ return;
+ }
#if notyet
if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) {
aprint_error(": couldn't get cs registers\n");
@@ -172,6 +179,12 @@
aprint_error(": couldn't map afi registers: %d\n", error);
return;
}
+ error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0,
+ &sc->sc_bsh_pads);
+ if (error) {
+ aprint_error(": couldn't map afi registers: %d\n", error);
+ return;
+ }
error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0,
&sc->sc_bsh_rpconf);
if (error) {
@@ -187,6 +200,9 @@
aprint_naive("\n");
aprint_normal(": PCIE\n");
+ tegra_pmc_power(PMC_PARTID_PCX, true);
+ tegra_pmc_remove_clamping(PMC_PARTID_PCX);
+
tegra_pcie_enable_clocks(sc);
if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
@@ -232,6 +248,8 @@
tegra_pcie_enable(sc);
+ tegra_pcie_enable_ports(sc);
+
memset(&pba, 0, sizeof(pba));
pba.pba_flags = PCI_FLAGS_MRL_OKAY |
PCI_FLAGS_MRM_OKAY |
@@ -338,10 +356,108 @@
}
static void
+tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index)
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