[src/trunk]: src/sys/arch/arm/nvidia use CLK_GATE_SIMPLE

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/76ac8328048a
branches:  trunk
changeset: 826766:76ac8328048a
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Thu Sep 28 09:44:29 2017 +0000

description:
use CLK_GATE_SIMPLE

diffstat:

 sys/arch/arm/nvidia/tegra210_car.c |  20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

diffs (42 lines):

diff -r 08fb45df1b91 -r 76ac8328048a sys/arch/arm/nvidia/tegra210_car.c
--- a/sys/arch/arm/nvidia/tegra210_car.c        Thu Sep 28 06:55:08 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_car.c        Thu Sep 28 09:44:29 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_car.c,v 1.16 2017/09/27 10:50:06 jmcneill Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.17 2017/09/28 09:44:29 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.16 2017/09/27 10:50:06 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.17 2017/09/28 09:44:29 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -594,15 +594,15 @@
        CLK_DIV("DIV_HDA", "MUX_HDA",
                CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV),
 
-       CLK_GATE("PLL_U_OUT1", "DIV_PLL_U_OUT1",
-                CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN),
-       CLK_GATE("PLL_U_OUT2", "DIV_PLL_U_OUT2",
-                CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN),
+       CLK_GATE_SIMPLE("PLL_U_OUT1", "DIV_PLL_U_OUT1",
+                CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN),
+       CLK_GATE_SIMPLE("PLL_U_OUT2", "DIV_PLL_U_OUT2",
+                CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN),
 
-       CLK_GATE("CML0", "PLL_E",
-                CAR_PLLE_AUX_REG, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN),
-       CLK_GATE("CML1", "PLL_E",
-                CAR_PLLE_AUX_REG, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN),
+       CLK_GATE_SIMPLE("CML0", "PLL_E",
+                CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN),
+       CLK_GATE_SIMPLE("CML1", "PLL_E",
+                CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN),
 
        CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA),
        CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB),