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[src/trunk]: src/sys/arch/arm/cortex Add GICv3 support.
details: https://anonhg.NetBSD.org/src/rev/eb5da4bca814
branches: trunk
changeset: 834320:eb5da4bca814
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Wed Aug 08 19:02:28 2018 +0000
description:
Add GICv3 support.
diffstat:
sys/arch/arm/cortex/files.cortex | 6 +-
sys/arch/arm/cortex/gicv3.c | 546 +++++++++++++++++++++++++++++++++++++++
sys/arch/arm/cortex/gicv3.h | 51 +++
3 files changed, 602 insertions(+), 1 deletions(-)
diffs (truncated from 625 to 300 lines):
diff -r ad8b5a442f85 -r eb5da4bca814 sys/arch/arm/cortex/files.cortex
--- a/sys/arch/arm/cortex/files.cortex Wed Aug 08 19:01:54 2018 +0000
+++ b/sys/arch/arm/cortex/files.cortex Wed Aug 08 19:02:28 2018 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.7 2018/06/05 08:03:28 hkenken Exp $
+# $NetBSD: files.cortex,v 1.8 2018/08/08 19:02:28 jmcneill Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -16,6 +16,10 @@
attach armgic at mpcorebus
file arch/arm/cortex/gic.c armgic
+# ARM Generic Interrupt Controller v3+
+device gicvthree: pic, pic_splfuncs
+file arch/arm/cortex/gicv3.c gicvthree
+
# ARM PL310 L2 Cache Controller(initially on Cortex-A9)
device arml2cc
attach arml2cc at mpcorebus
diff -r ad8b5a442f85 -r eb5da4bca814 sys/arch/arm/cortex/gicv3.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/cortex/gicv3.c Wed Aug 08 19:02:28 2018 +0000
@@ -0,0 +1,546 @@
+/* $NetBSD: gicv3.c,v 1.1 2018/08/08 19:02:28 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_multiprocessor.h"
+
+#define _INTR_PRIVATE
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.1 2018/08/08 19:02:28 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/cpu.h>
+
+#include <arm/locore.h>
+#include <arm/armreg.h>
+
+#include <arm/cortex/gicv3.h>
+#include <arm/cortex/gic_reg.h>
+
+#define PICTOSOFTC(pic) \
+ ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic)))
+
+#define IPL_TO_PRIORITY(ipl) ((IPL_HIGH - (ipl)) << 4)
+
+static struct gicv3_softc *gicv3_softc;
+
+static inline uint32_t
+gicd_read_4(struct gicv3_softc *sc, bus_size_t reg)
+{
+ return bus_space_read_4(sc->sc_bst, sc->sc_bsh_d, reg);
+}
+
+static inline void
+gicd_write_4(struct gicv3_softc *sc, bus_size_t reg, uint32_t val)
+{
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_d, reg, val);
+}
+
+static inline void
+gicd_write_8(struct gicv3_softc *sc, bus_size_t reg, uint64_t val)
+{
+ bus_space_write_8(sc->sc_bst, sc->sc_bsh_d, reg, val);
+}
+
+static inline uint32_t
+gicr_read_4(struct gicv3_softc *sc, u_int index, bus_size_t reg)
+{
+ KASSERT(index < sc->sc_bsh_r_count);
+ return bus_space_read_4(sc->sc_bst, sc->sc_bsh_r[index], reg);
+}
+
+static inline void
+gicr_write_4(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint32_t val)
+{
+ KASSERT(index < sc->sc_bsh_r_count);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh_r[index], reg, val);
+}
+
+static inline uint64_t
+gicr_read_8(struct gicv3_softc *sc, u_int index, bus_size_t reg)
+{
+ KASSERT(index < sc->sc_bsh_r_count);
+ return bus_space_read_8(sc->sc_bst, sc->sc_bsh_r[index], reg);
+}
+
+static inline void
+gicr_write_8(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint64_t val)
+{
+ KASSERT(index < sc->sc_bsh_r_count);
+ bus_space_write_8(sc->sc_bst, sc->sc_bsh_r[index], reg, val);
+}
+
+static void
+gicv3_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask)
+{
+ struct gicv3_softc * const sc = PICTOSOFTC(pic);
+ struct cpu_info * const ci = curcpu();
+ const u_int group = irqbase / 32;
+
+ if (group == 0) {
+ sc->sc_enabled_sgippi |= mask;
+ gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, mask);
+ while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTRL) & GICR_CTRL_RWP)
+ ;
+ } else {
+ gicd_write_4(sc, GICD_ISENABLERn(group), mask);
+ while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP)
+ ;
+ }
+}
+
+static void
+gicv3_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask)
+{
+ struct gicv3_softc * const sc = PICTOSOFTC(pic);
+ struct cpu_info * const ci = curcpu();
+ const u_int group = irqbase / 32;
+
+ if (group == 0) {
+ sc->sc_enabled_sgippi &= ~mask;
+ gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, mask);
+ while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTRL) & GICR_CTRL_RWP)
+ ;
+ } else {
+ gicd_write_4(sc, GICD_ICENABLERn(group), mask);
+ while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP)
+ ;
+ }
+}
+
+static void
+gicv3_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
+ struct gicv3_softc * const sc = PICTOSOFTC(pic);
+ const u_int group = is->is_irq / 32;
+ uint32_t ipriority, icfg;
+ uint64_t irouter;
+ u_int n;
+
+ const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
+ const u_int icfg_shift = (is->is_irq & 0xf) * 2;
+
+ if (group == 0) {
+ /* SGIs and PPIs are always MP-safe */
+ is->is_mpsafe = true;
+
+ /* Update interrupt configuration and priority on all redistributors */
+ for (n = 0; n < sc->sc_bsh_r_count; n++) {
+ icfg = gicr_read_4(sc, n, GICR_ICFGRn(is->is_irq / 16));
+ if (is->is_type == IST_LEVEL)
+ icfg &= ~(0x2 << icfg_shift);
+ if (is->is_type == IST_EDGE)
+ icfg |= (0x2 << icfg_shift);
+ gicr_write_4(sc, n, GICR_ICFGRn(is->is_irq / 16), icfg);
+
+ ipriority = gicr_read_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4));
+ ipriority &= ~(0xff << ipriority_shift);
+ ipriority |= (IPL_TO_PRIORITY(is->is_ipl) << ipriority_shift);
+ gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
+ }
+ } else {
+ if (is->is_mpsafe) {
+ /* Route MP-safe interrupts to all participating PEs */
+ irouter = GICD_IROUTER_Interrupt_Routing_mode;
+ } else {
+ /* Route non-MP-safe interrupts to the primary PE only */
+ irouter = sc->sc_default_irouter;
+ }
+ gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter);
+
+ /* Update interrupt configuration */
+ icfg = gicd_read_4(sc, GICD_ICFGRn(is->is_irq / 16));
+ if (is->is_type == IST_LEVEL)
+ icfg &= ~(0x2 << icfg_shift);
+ if (is->is_type == IST_EDGE)
+ icfg |= (0x2 << icfg_shift);
+ gicd_write_4(sc, GICD_ICFGRn(is->is_irq / 16), icfg);
+
+ /* Update interrupt priority */
+ ipriority = gicd_read_4(sc, GICD_IPRIORITYRn(is->is_irq / 4));
+ ipriority &= ~(0xff << ipriority_shift);
+ ipriority |= (IPL_TO_PRIORITY(is->is_ipl) << ipriority_shift);
+ gicd_write_4(sc, GICD_IPRIORITYRn(is->is_irq / 4), ipriority);
+ }
+}
+
+static void
+gicv3_set_priority(struct pic_softc *pic, int ipl)
+{
+ icc_pmr_write(IPL_TO_PRIORITY(ipl));
+}
+
+static void
+gicv3_dist_enable(struct gicv3_softc *sc)
+{
+ uint32_t gicd_ctrl;
+ u_int n;
+
+ /* Disable the distributor */
+ gicd_write_4(sc, GICD_CTRL, 0);
+
+ /* Wait for register write to complete */
+ while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP)
+ ;
+
+ /* Clear all INTID enable bits */
+ for (n = 32; n < sc->sc_pic.pic_maxsources; n += 32)
+ gicd_write_4(sc, GICD_ICENABLERn(n / 32), ~0);
+
+ /* Set default priorities to lowest */
+ for (n = 32; n < sc->sc_pic.pic_maxsources; n += 4)
+ gicd_write_4(sc, GICD_IPRIORITYRn(n / 4), ~0);
+
+ /* Set all interrupts to G1NS */
+ for (n = 32; n < sc->sc_pic.pic_maxsources; n += 32) {
+ gicd_write_4(sc, GICD_IGROUPRn(n / 32), ~0);
+ gicd_write_4(sc, GICD_IGRPMODRn(n / 32), 0);
+ }
+
+ /* Set all interrupts level-sensitive by default */
+ for (n = 32; n < sc->sc_pic.pic_maxsources; n += 16)
+ gicd_write_4(sc, GICD_ICFGRn(n / 16), 0);
+
+ /* Wait for register writes to complete */
+ while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP)
+ ;
+
+ /* Enable Affinity routing and G1NS interrupts */
+ gicd_ctrl = GICD_CTRL_EnableGrp1NS | GICD_CTRL_Enable | GICD_CTRL_ARE_NS;
+ gicd_write_4(sc, GICD_CTRL, gicd_ctrl);
+}
+
+static void
+gicv3_redist_enable(struct gicv3_softc *sc, struct cpu_info *ci)
+{
+ uint32_t icfg;
+ u_int n, o;
+
+ /* Clear INTID enable bits */
+ gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, ~0);
+
+ /* Wait for register write to complete */
+ while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTRL) & GICR_CTRL_RWP)
+ ;
+
+ /* Set default priorities */
+ for (n = 0; n < 32; n += 4) {
+ uint32_t priority = 0;
+ size_t byte_shift = 0;
+ for (o = 0; o < 4; o++, byte_shift += 8) {
+ struct intrsource * const is = sc->sc_pic.pic_sources[n + o];
+ if (is == NULL)
+ priority |= 0xff << byte_shift;
+ else
+ priority |= IPL_TO_PRIORITY(is->is_ipl) << byte_shift;
+ }
+ gicr_write_4(sc, ci->ci_gic_redist, GICR_IPRIORITYRn(n / 4), priority);
+ }
+
+ /* Set all interrupts to G1NS */
+ gicr_write_4(sc, ci->ci_gic_redist, GICR_IGROUPR0, ~0);
+ gicr_write_4(sc, ci->ci_gic_redist, GICR_IGRPMODR0, 0);
+
+ /* Restore PPI configs */
+ for (n = 0, icfg = 0; n < 16; n++) {
+ struct intrsource * const is = sc->sc_pic.pic_sources[16 + n];
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