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[src/trunk]: src/sys/arch/arm/arm More instructions. Lots left to do.
details: https://anonhg.NetBSD.org/src/rev/b7da88068c57
branches: trunk
changeset: 807200:b7da88068c57
user: skrll <skrll%NetBSD.org@localhost>
date: Tue Mar 31 16:15:07 2015 +0000
description:
More instructions. Lots left to do.
diffstat:
sys/arch/arm/arm/disassem.c | 319 ++++++++++++++++++++++++++++++++++---------
1 files changed, 252 insertions(+), 67 deletions(-)
diffs (truncated from 486 to 300 lines):
diff -r 5390808a104b -r b7da88068c57 sys/arch/arm/arm/disassem.c
--- a/sys/arch/arm/arm/disassem.c Tue Mar 31 15:49:45 2015 +0000
+++ b/sys/arch/arm/arm/disassem.c Tue Mar 31 16:15:07 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: disassem.c,v 1.31 2015/01/18 18:23:25 skrll Exp $ */
+/* $NetBSD: disassem.c,v 1.32 2015/03/31 16:15:07 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@@ -49,7 +49,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.31 2015/01/18 18:23:25 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disassem.c,v 1.32 2015/03/31 16:15:07 skrll Exp $");
#include <sys/systm.h>
@@ -71,16 +71,21 @@
* the instruction. The only exception is the writeback flag which
* follows a operand.
*
- *
+ * !c - cps flags and mode
+ * !d - debug option (bit 0-3)
+ * !l - dmb/dsb limitation
+ * !m - mode
* 2 - print Operand 2 of a data processing instruction
* a - address operand of ldr/str instruction
* b - branch address
* c - comment field bits(0-23)
* d - destination register (bits 12-15)
- * e - address operand of ldrh/strh instruction
+ * e - address operand of ldrx/strx instruction
* f - 1st fp operand (register) (bits 12-14)
* g - 2nd fp operand (register) (bits 16-18)
* h - 3rd fp operand (register/immediate) (bits 0-4)
+ * i - lsb operand (bits 7-11)
+ * j - msb operand (bits 6,7,12-14)
* k - breakpoint comment (bits 0-3, 8-19)
* l - register list for ldm/stm instruction
* m - m register (bits 0-3)
@@ -88,6 +93,7 @@
* o - indirect register rn (bits 16-19) (used by swap)
* p - saved or current status register
* q - neon N register (7, 19-16)
+ * r - width minus 1 (bits 16-20)
* s - s register (bits 8-11)
* t - thumb branch address (bits 24, 0-23)
* u - neon M register (5, 3-0)
@@ -96,6 +102,7 @@
* x - instruction in hex
* y - co-processor data processing registers
* z - co-processor register transfer registers
+ * C - cps effect
* D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN
* F - PSR transfer fields
* I - NEON operand size
@@ -121,60 +128,128 @@
};
static const struct arm32_insn arm32_i[] = {
- { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
- { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
- { 0x0fffffff, 0x0320f003, "yield", "" }, /* Before swi */
- { 0x0fffffff, 0x0320f002, "wfe", "" }, /* Before swi */
- { 0x0fffffff, 0x0320f003, "wfi", "" }, /* Before swi */
- { 0x0f000000, 0x0f000000, "swi", "c" },
+ /* A5.7 Unconditional instructions */
+ /*
+ * A5.7.1 Memory hints, Advanced SIMD instructions, and
+ * miscellaneous instructions
+ */
+ { 0xfff10020, 0xf1000000, "cps", "C!c" },
+ { 0xfff100f0, 0xf1010000, "setend\tle", "" },
+ { 0xfff102f0, 0xf1010200, "setend\tbe", "" },
+/* pli */
+/* pld */
+ { 0xffffffff, 0xf57ff01f, "clrex", "" },
+ { 0xfffffff0, 0xf57ff040, "dsb", "!l" },
+ { 0xfffffff0, 0xf57ff050, "dmb", "!l" },
+ { 0xfffffff0, 0xf57ff060, "isb", "" },
+/* pli */
+/* pld */
+
+ //{ 0x0e100000, 0x08000000, "stm", "XnWl" },
+ { 0xfe5fffe0, 0xf84d0500, "srs", "XnW!m" },
+ { 0xfe50ffff, 0xf8100a00, "rfe", "XnW" },
{ 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
- { 0x0f000000, 0x0a000000, "b", "b" },
- { 0x0f000000, 0x0b000000, "bl", "b" },
- { 0x0fe000f0, 0x00000090, "mul", "Snms" },
- { 0x0fe000f0, 0x00200090, "mla", "Snmsd" },
- { 0x0fe000f0, 0x00800090, "umull", "Sdnms" },
- { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" },
- { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" },
- { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" },
+ { 0xfe100090, 0xfc000000, "stc2", "L#v" },
+ { 0x0e100090, 0x0c000000, "stc", "L#v" },
+ { 0xfe100090, 0xfc100000, "ldc2", "L#v" },
+ { 0x0e100090, 0x0c100000, "ldc", "L#v" },
+ { 0x0ff00000, 0x0c400000, "mcrr", "#&" },
+ { 0x0ff00000, 0x0c500000, "mrrc", "#&" },
+ { 0xff000010, 0xfe000000, "cdp2", "#y" },
+ { 0x0f000010, 0x0e000000, "cdp", "#y" },
+ { 0xff100010, 0xfe000010, "mcr2", "#z" },
+ { 0x0f100010, 0x0e000010, "mcr", "#z" },
+ { 0xff100010, 0xfe100010, "mrc2", "#z" },
+ { 0x0f100010, 0x0e100010, "mrc", "#z" },
+
+ /* A5.4 Media instructions */
+ { 0x0fe00070, 0x07c00050, "sbfx", "dmir" },
+ { 0x0fe0007f, 0x07c0001f, "bfc", "dij" },
+ { 0x0fe00070, 0x07c00010, "bfi", "dmij" },
+ { 0x0fe00070, 0x07e00050, "ubfx", "dmir" },
+ { 0xfff000f0, 0xe70000f0, "und", "x" }, /* Special immediate? */
+
+ { 0x06000010, 0x06000010, "und", "x" }, /* Remove when done with media */
+
{ 0x0d700000, 0x04200000, "strt", "daW" },
{ 0x0d700000, 0x04300000, "ldrt", "daW" },
{ 0x0d700000, 0x04600000, "strbt", "daW" },
{ 0x0d700000, 0x04700000, "ldrbt", "daW" },
+
{ 0x0c500000, 0x04000000, "str", "daW" },
{ 0x0c500000, 0x04100000, "ldr", "daW" },
{ 0x0c500000, 0x04400000, "strb", "daW" },
{ 0x0c500000, 0x04500000, "ldrb", "daW" },
+
+
+ /* A5.5 Branch, branch with link, and block data transfer */
{ 0x0fff0000, 0x092d0000, "push", "l" }, /* separate out r13 base */
{ 0x0fff0000, 0x08bd0000, "pop", "l" }, /* separate out r13 base */
{ 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */
{ 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */
{ 0x0e100000, 0x08000000, "stm", "XnWl" },
{ 0x0e100000, 0x08100000, "ldm", "XnWl" },
- { 0x0ff00fff, 0x01900f9f, "ldrex", "da" },
- { 0x0ff00fff, 0x01b00f9f, "ldrexd", "da" },
- { 0x0ff00fff, 0x01d00f9f, "ldrexb", "da" },
- { 0x0ff00fff, 0x01f00f9f, "ldrexh", "da" },
- { 0x0ff00ff0, 0x01800f90, "strex", "dma" },
- { 0x0ff00ff0, 0x01a00f90, "strexd", "dma" },
- { 0x0ff00ff0, 0x01c00f90, "strexb", "dma" },
- { 0x0ff00ff0, 0x01e00f90, "strexh", "dma" },
- { 0x0e1000f0, 0x001000d0, "ldrsb", "de" },
+ { 0x0f000000, 0x0a000000, "b", "b" },
+ { 0x0f000000, 0x0b000000, "bl", "b" },
+
+ { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
+ { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
+ { 0x0f000000, 0x0f000000, "swi", "c" },
+
+ /*
+ * A5.2 Data-process and miscellaneous instructions
+ */
+
+ /* A5.2 exceptions */
+
+ /* A5.2.7 Halfword multiply and multiply accumulate */
+
+ /* A5.2.8 Extra load/store instructions */
+
+ { 0x0e1000f0, 0x000000b0, "strh", "de" },
{ 0x0e1000f0, 0x001000b0, "ldrh", "de" },
- { 0x0e1000f0, 0x000000b0, "strh", "de" },
+
+ { 0x0e5000f0, 0x000000d0, "ldrd", "de" },
+ { 0x0e5000f0, 0x001000d0, "ldrsb", "de" },
+ { 0x0e5000f0, 0x004000d0, "ldrd", "de" },
+ { 0x0e5000f0, 0x005000d0, "ldrsb", "de" },
+
+ { 0x0e1000f0, 0x000000f0, "ldrd", "de" },
+ { 0x0e1000f0, 0x001000f0, "ldrsb", "de" },
+ { 0x0e1000f0, 0x000000f0, "strd", "de" },
{ 0x0e1000f0, 0x001000f0, "ldrsh", "de" },
- { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */
- { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */
- { 0x0ff00ff0, 0x01000090, "swp", "dmo" },
- { 0x0ff00ff0, 0x01400090, "swpb", "dmo" },
- { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */
- { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */
- { 0x0fe0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */
+
+ /* A5.2.11 MSR (immediate), and hints */
+ { 0x0fffffff, 0x0320f000, "nop", "" },
+ { 0x0fffffff, 0x0320f001, "yield", "" },
+ { 0x0fffffff, 0x0320f002, "wfe", "" },
+ { 0x0fffffff, 0x0320f003, "wfi", "" },
+ { 0x0fffffff, 0x0320f004, "sev", "" },
+ { 0x0ffffff0, 0x0320f0f0, "dbg", "!d" },
+
+ /* A5.2.12 Miscellaneous instructions - before data processing */
+
+ { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* A8.8.109, B9.3.8 */
+ { 0x0fb00eff, 0x01000200, "mrs", "c" }, /* XXXNH: B9.3.9 */
+ { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },
+ { 0x0fe0f000, 0x0320f000, "msr", "pF2" },
+
{ 0x0ffffff0, 0x012fff10, "bx", "m" },
{ 0x0fff0ff0, 0x016f0f10, "clz", "dm" },
+/* bxj */
{ 0x0ffffff0, 0x012fff30, "blx", "m" },
+/* saturating */
+/* eret */
{ 0xfff000f0, 0xe1200070, "bkpt", "k" },
+/* hvc */
+/* smc */
+
{ 0x0ff00000, 0x03000000, "movw", "dZ" },
{ 0x0ff00000, 0x03400000, "movt", "dZ" },
+
+ /* A5.2 non-exceptions */
+
+ /* A5.2.1, A5.2.2, and A5.2.3 Data-processing */
{ 0x0de00000, 0x00000000, "and", "Sdn2" },
{ 0x0de00000, 0x00200000, "eor", "Sdn2" },
{ 0x0de00000, 0x00400000, "sub", "Sdn2" },
@@ -191,6 +266,28 @@
{ 0x0de00000, 0x01a00000, "mov", "Sd2" },
{ 0x0de00000, 0x01c00000, "bic", "Sdn2" },
{ 0x0de00000, 0x01e00000, "mvn", "Sd2" },
+
+ /* A5.2.5 Multiply and multiply accumulate */
+ { 0x0fe000f0, 0x00000090, "mul", "Snms" },
+ { 0x0fe000f0, 0x00200090, "mla", "Snmsd" },
+ { 0x0fe000f0, 0x00800090, "umull", "Sdnms" },
+ { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" },
+ { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" },
+ { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" },
+
+ /* A5.2.10 Synchronisation primitives */
+ { 0x0ff00ff0, 0x01000090, "swp", "dmo" },
+ { 0x0ff00ff0, 0x01400090, "swpb", "dmo" },
+ { 0x0ff00fff, 0x01900f9f, "ldrex", "da" },
+ { 0x0ff00fff, 0x01b00f9f, "ldrexd", "da" },
+ { 0x0ff00fff, 0x01d00f9f, "ldrexb", "da" },
+ { 0x0ff00fff, 0x01f00f9f, "ldrexh", "da" },
+ { 0x0ff00ff0, 0x01800f90, "strex", "dma" },
+ { 0x0ff00ff0, 0x01a00f90, "strexd", "dma" },
+ { 0x0ff00ff0, 0x01c00f90, "strexb", "dma" },
+ { 0x0ff00ff0, 0x01e00f90, "strexh", "dma" },
+
+ /* */
{ 0x0ff08f10, 0x0e000100, "adf", "PRfgh" },
{ 0x0ff08f10, 0x0e100100, "muf", "PRfgh" },
{ 0x0ff08f10, 0x0e200100, "suf", "PRfgh" },
@@ -232,18 +329,7 @@
{ 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" },
{ 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" },
{ 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" },
- { 0xff100010, 0xfe000010, "mcr2", "#z" },
- { 0x0f100010, 0x0e000010, "mcr", "#z" },
- { 0xff100010, 0xfe100010, "mrc2", "#z" },
- { 0x0f100010, 0x0e100010, "mrc", "#z" },
- { 0xff000010, 0xfe000000, "cdp2", "#y" },
- { 0x0f000010, 0x0e000000, "cdp", "#y" },
- { 0x0ff00000, 0x0c400000, "mcrr", "#&" },
- { 0x0ff00000, 0x0c500000, "mrrc", "#&" },
- { 0xfe100090, 0xfc100000, "ldc2", "L#v" },
- { 0x0e100090, 0x0c100000, "ldc", "L#v" },
- { 0xfe100090, 0xfc000000, "stc2", "L#v" },
- { 0x0e100090, 0x0c000000, "stc", "L#v" },
+
{ 0xffb00f10, 0xf2000110, "vand", "Nuqw" },
{ 0xffb00f10, 0xf2100110, "vbic", "Nuqw" },
{ 0xffb00f10, 0xf2200110, "vorr", "Nuqw" },
@@ -282,6 +368,25 @@
"lsl", "lsr", "asr", "ror"
};
+static char const *insn_barrier_limiation[] = {
+ "",
+ "",
+ "oshst", /* 0b0010 */
+ "osh", /* 0b0011 */
+ "",
+ "",
+ "nshst", /* 0b0110 */
+ "nsh", /* 0b0111 */
+ "",
+ "",
+ "ishst", /* 0b1010 */
+ "ish", /* 0b1011 */
+ "",
+ "",
+ "st", /* 0b1110 */
+ "sy", /* 0b1111 */
+};
+
static char const insn_fpa_rounding[][2] = {
"", "p", "m", "z"
};
@@ -298,6 +403,7 @@
#define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f]
#define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3]
#define insn_stkblktrans(x) insn_stack_block_transfers[((x >> (20 - 2)) & 4)|((x >> 23) & 3)]
+#define insn_limitation(x) insn_barrier_limiation[x & 0xf]
#define op2_shift(x) op_shifts[(x >> 5) & 3]
#define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03]
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