[src/trunk]: src/sys/arch/mips/mips Set mci_{, i}cache_alias_mask for all vari...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/690bb4cd439b
branches:  trunk
changeset: 823909:690bb4cd439b
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sun May 14 09:37:13 2017 +0000

description:
Set mci_{,i}cache_alias_mask for all variants that can have virtual cache
aliases

Set ncolors appropriately

These align to dcache and expect icache aliases to be dealt with by the
pmap directly.

diffstat:

 sys/arch/mips/mips/cache.c |  24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

diffs (65 lines):

diff -r d53ae4da1950 -r 690bb4cd439b sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c        Sun May 14 09:33:17 2017 +0000
+++ b/sys/arch/mips/mips/cache.c        Sun May 14 09:37:13 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.57 2017/05/14 09:33:17 skrll Exp $ */
+/*     $NetBSD: cache.c,v 1.58 2017/05/14 09:37:13 skrll Exp $ */
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.57 2017/05/14 09:33:17 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.58 2017/05/14 09:37:13 skrll Exp $");
 
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
@@ -662,7 +662,7 @@
                KASSERT(mci->mci_picache_ways != 0);
                mci->mci_picache_way_size = mci->mci_picache_size / mci->mci_picache_ways;
                mci->mci_picache_way_mask = mci->mci_picache_way_size - 1;
-#if (MIPS2 + MIPS3) > 0
+#if (MIPS2 + MIPS3 + MIPS4) > 0
                if (mci->mci_icache_virtual_alias)
                        mci->mci_icache_alias_mask =
                            mci->mci_picache_way_mask & -PAGE_SIZE;
@@ -672,13 +672,21 @@
                KASSERT(mci->mci_pdcache_ways != 0);
                mci->mci_pdcache_way_size = mci->mci_pdcache_size / mci->mci_pdcache_ways;
                mci->mci_pdcache_way_mask = mci->mci_pdcache_way_size - 1;
-#if (MIPS2 + MIPS3) > 0
+#if (MIPS2 + MIPS3 + MIPS4) > 0
                if (mci->mci_cache_virtual_alias)
                        mci->mci_cache_alias_mask =
                            mci->mci_pdcache_way_mask & -PAGE_SIZE;
 #endif
        }
 
+#if (MIPS2 + MIPS3 + MIPS4) > 0
+       if (mci->mci_cache_virtual_alias) {
+               mci->mci_cache_prefer_mask = mci->mci_pdcache_way_mask;
+
+               uvmexp.ncolors = (mci->mci_cache_prefer_mask >> PAGE_SHIFT) + 1;
+       }
+#endif
+
        mips_dcache_compute_align();
 
        if (mci->mci_sdcache_line_size == 0)
@@ -987,14 +995,6 @@
        mci->mci_pdcache_line_size = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
            MIPS3_CONFIG_DB);
 
-       mci->mci_icache_alias_mask =
-           (mci->mci_picache_size / mci->mci_picache_ways - 1) & -PAGE_SIZE;
-       mci->mci_cache_alias_mask =
-           (mci->mci_pdcache_size / mci->mci_pdcache_ways - 1) & -PAGE_SIZE;
-       mci->mci_cache_prefer_mask =
-           max(mci->mci_pdcache_size, mci->mci_picache_size) - 1;
-       uvmexp.ncolors = (mci->mci_cache_alias_mask >> PAGE_SHIFT) + 1;
-
        switch(MIPS_PRID_IMPL(cpu_id)) {
 #ifndef ENABLE_MIPS_R3NKK
        case MIPS_R5000: