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[src/netbsd-9]: src/sys Pull up following revision(s) (requested by jmcneill ...
details: https://anonhg.NetBSD.org/src/rev/6c787f9522b2
branches: netbsd-9
changeset: 843567:6c787f9522b2
user: martin <martin%NetBSD.org@localhost>
date: Mon Nov 25 16:18:40 2019 +0000
description:
Pull up following revision(s) (requested by jmcneill in ticket #470):
sys/arch/arm/sunxi/sunxi_hdmiphy.c: revision 1.4
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.16
sys/dev/ic/dw_hdmi.c: revision 1.5
sys/arch/arm/sunxi/sunxi_hdmiphy.h: revision 1.2
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.17
sys/dev/ic/dw_hdmi.c: revision 1.6
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.18
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.19
sys/dev/ic/dw_hdmi.h: revision 1.5
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.8
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.9
sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.22
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.5
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.6
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.7
sys/arch/arm/sunxi/sunxi_dwhdmi.c: revision 1.8
sys/arch/arm/sunxi/sun50i_a64_ccu.c: revision 1.20
sys/arch/arm/sunxi/sunxi_mixer.c: revision 1.10
sys/arch/arm/dts/sun50i-a64-pinebook.dts: revision 1.17
sys/arch/arm/sunxi/sunxi_platform.c: revision 1.38
sys/dev/fdt/fdt_port.c: revision 1.3
sys/dev/fdt/fdt_port.c: revision 1.4
sys/arch/arm/sunxi/sunxi_ccu_fractional.c: revision 1.5
sys/arch/arm/sunxi/sunxi_lcdc.c: revision 1.7
sys/arch/arm/sunxi/sunxi_ccu_fractional.c: revision 1.6
sys/arch/arm/sunxi/sunxi_hdmiphy.c: revision 1.3
Fix CLK_BUS_HDMI bit
Enable TMDS clock
Store the flags passed to SUNXI_CCU_FRACTIONAL macro.
Previously the macro dropped the flags argument entirely, and did not
initialize the structure with it.
Allow bus glue to setup DDC clocks
Add TCON0 clock
HDMI PHY and TX share the same clocks. Do not enable clocks until both
reset resources have been deasserted. Explicitly set DDC clock dividers.
Honour SUNXI_CCU_FRACTIONAL_SET_ENABLE in fractional mode
Use fdtbus_get_reg to read "reg" property
Need to initialize the PHY before HPD sense and DDC will work
Set pixel clock on mode set
Set TCON1 parent to PLL_VIDEO1(1X)
Do not assume that an fb's pitch is width * 4 bytes.
Use actual hw mode, not proposed mode.
Set pre-divider M to 0 in fractional mode, as noted in user manual. Spotted by jak.
Support non-zero fb start pixels.
Set video PLLs to 297MHz
Do not assume the cursor pitch is the same as the primary fb
Enable HDMI and HDMI audio
Try to avoid changing hardware settings when the "nomodeset" kernel arg
is present.
diffstat:
sys/arch/arm/dts/sun50i-a64-pinebook.dts | 38 ++++++++++++++++++-
sys/arch/arm/sunxi/sun50i_a64_ccu.c | 37 +++++++++++++++---
sys/arch/arm/sunxi/sunxi_ccu.h | 3 +-
sys/arch/arm/sunxi/sunxi_ccu_fractional.c | 7 ++-
sys/arch/arm/sunxi/sunxi_dwhdmi.c | 62 +++++++++++++++++++++++-------
sys/arch/arm/sunxi/sunxi_hdmiphy.c | 54 ++++++++++++++-------------
sys/arch/arm/sunxi/sunxi_hdmiphy.h | 3 +-
sys/arch/arm/sunxi/sunxi_lcdc.c | 47 +++++++++++------------
sys/arch/arm/sunxi/sunxi_mixer.c | 17 +++++---
sys/arch/arm/sunxi/sunxi_platform.c | 12 ++++-
sys/dev/fdt/fdt_port.c | 8 ++--
sys/dev/ic/dw_hdmi.c | 28 +++++++++-----
sys/dev/ic/dw_hdmi.h | 4 +-
13 files changed, 219 insertions(+), 101 deletions(-)
diffs (truncated from 774 to 300 lines):
diff -r b2c8c1454886 -r 6c787f9522b2 sys/arch/arm/dts/sun50i-a64-pinebook.dts
--- a/sys/arch/arm/dts/sun50i-a64-pinebook.dts Mon Nov 25 05:52:54 2019 +0000
+++ b/sys/arch/arm/dts/sun50i-a64-pinebook.dts Mon Nov 25 16:18:40 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun50i-a64-pinebook.dts,v 1.16 2019/06/06 23:19:45 jmcneill Exp $ */
+/* $NetBSD: sun50i-a64-pinebook.dts,v 1.16.2.1 2019/11/25 16:18:40 martin Exp $ */
/*-
* Copyright (c) 2017-2019 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -54,6 +54,17 @@
sound_spdif {
status = "disabled";
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
};
&cpu0 {
@@ -151,3 +162,28 @@
};
};
};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2s2 {
+ status = "okay";
+};
+
+&sound_hdmi {
+ status = "okay";
+};
diff -r b2c8c1454886 -r 6c787f9522b2 sys/arch/arm/sunxi/sun50i_a64_ccu.c
--- a/sys/arch/arm/sunxi/sun50i_a64_ccu.c Mon Nov 25 05:52:54 2019 +0000
+++ b/sys/arch/arm/sunxi/sun50i_a64_ccu.c Mon Nov 25 16:18:40 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun50i_a64_ccu.c,v 1.13.2.2 2019/11/18 19:36:03 martin Exp $ */
+/* $NetBSD: sun50i_a64_ccu.c,v 1.13.2.3 2019/11/25 16:18:40 martin Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.13.2.2 2019/11/18 19:36:03 martin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.13.2.3 2019/11/25 16:18:40 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -69,6 +69,7 @@
#define DRAM_CFG_REG 0x0f4
#define MBUS_RST_REG 0x0fc
#define DE_CLK_REG 0x104
+#define TCON0_CLK_REG 0x118
#define TCON1_CLK_REG 0x11c
#define AC_DIG_CLK_REG 0x140
#define HDMI_CLK_REG 0x150
@@ -161,6 +162,7 @@
static const char *hdmi_parents[] = { "pll_video0", "pll_video1" };
static const char *i2s_parents[] = { "pll_audio_8x", "pll_audio_4x", "pll_audio_2x", "pll_audio" };
static const char *spi_parents[] = { "hosc", "pll_periph0", "pll_periph1", NULL };
+static const char *tcon0_parents[] = { "pll_mipi", NULL, "pll_video0_2x", NULL };
static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL };
static const char *gpu_parents[] = { "pll_gpu" };
@@ -459,6 +461,13 @@
__BIT(31), /* enable */
SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_DIV_GATE(A64_CLK_TCON0, "tcon0", tcon0_parents,
+ TCON0_CLK_REG, /* reg */
+ 0, /* div */
+ __BITS(26,24), /* sel */
+ __BIT(31), /* enable */
+ 0),
+
SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents,
TCON1_CLK_REG, /* reg */
__BITS(3,0), /* div */
@@ -521,7 +530,7 @@
SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1",
BUS_CLK_GATING_REG1, 8),
SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1",
- BUS_CLK_GATING_REG1, 10),
+ BUS_CLK_GATING_REG1, 11),
SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1",
BUS_CLK_GATING_REG1, 12),
SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1",
@@ -592,6 +601,8 @@
{
struct sunxi_ccu_softc * const sc = device_private(self);
struct fdt_attach_args * const faa = aux;
+ prop_dictionary_t prop = device_properties(self);
+ bool nomodeset;
sc->sc_dev = self;
sc->sc_phandle = faa->faa_phandle;
@@ -609,9 +620,23 @@
aprint_naive("\n");
aprint_normal(": A64 CCU\n");
- /* Set DE parent to PLL_DE */
- clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base);
- clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000);
+ nomodeset = false;
+ prop_dictionary_get_bool(prop, "nomodeset", &nomodeset);
+ if (!nomodeset) {
+ /* Set DE parent to PLL_DE */
+ clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base);
+ clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000);
+
+ /* Set video PLLs to 297 MHz */
+ clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO0].base, 297000000);
+ clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO1].base, 297000000);
+
+ /* Set TCON1 parent to PLL_VIDEO1(1X) */
+ clk_set_parent(&sc->sc_clks[A64_CLK_TCON1].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base);
+
+ /* Set HDMI parent to PLL_VIDEO1(1X) */
+ clk_set_parent(&sc->sc_clks[A64_CLK_HDMI].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base);
+ }
sunxi_ccu_print(sc);
}
diff -r b2c8c1454886 -r 6c787f9522b2 sys/arch/arm/sunxi/sunxi_ccu.h
--- a/sys/arch/arm/sunxi/sunxi_ccu.h Mon Nov 25 05:52:54 2019 +0000
+++ b/sys/arch/arm/sunxi/sunxi_ccu.h Mon Nov 25 16:18:40 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_ccu.h,v 1.21 2019/01/30 01:24:00 jmcneill Exp $ */
+/* $NetBSD: sunxi_ccu.h,v 1.21.4.1 2019/11/25 16:18:40 martin Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -405,6 +405,7 @@
.u.fractional.frac[0] = (_frac0), \
.u.fractional.frac[1] = (_frac1), \
.u.fractional.enable = (_enable), \
+ .u.fractional.flags = (_flags), \
.enable = sunxi_ccu_fractional_enable, \
.get_rate = sunxi_ccu_fractional_get_rate, \
.set_rate = sunxi_ccu_fractional_set_rate, \
diff -r b2c8c1454886 -r 6c787f9522b2 sys/arch/arm/sunxi/sunxi_ccu_fractional.c
--- a/sys/arch/arm/sunxi/sunxi_ccu_fractional.c Mon Nov 25 05:52:54 2019 +0000
+++ b/sys/arch/arm/sunxi/sunxi_ccu_fractional.c Mon Nov 25 16:18:40 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_ccu_fractional.c,v 1.4 2019/01/30 01:24:00 jmcneill Exp $ */
+/* $NetBSD: sunxi_ccu_fractional.c,v 1.4.4.1 2019/11/25 16:18:40 martin Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_fractional.c,v 1.4 2019/01/30 01:24:00 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_fractional.c,v 1.4.4.1 2019/11/25 16:18:40 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -137,9 +137,12 @@
for (i = 0; i < __arraycount(fractional->frac); i++) {
if (fractional->frac[i] == new_rate) {
+ val &= ~fractional->prediv;
val &= ~fractional->div_en;
val &= ~fractional->frac_sel;
val |= __SHIFTIN(i, fractional->frac_sel);
+ if (fractional->flags & SUNXI_CCU_FRACTIONAL_SET_ENABLE)
+ val |= fractional->enable;
CCU_WRITE(sc, fractional->reg, val);
return 0;
}
diff -r b2c8c1454886 -r 6c787f9522b2 sys/arch/arm/sunxi/sunxi_dwhdmi.c
--- a/sys/arch/arm/sunxi/sunxi_dwhdmi.c Mon Nov 25 05:52:54 2019 +0000
+++ b/sys/arch/arm/sunxi/sunxi_dwhdmi.c Mon Nov 25 16:18:40 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_dwhdmi.c,v 1.3.6.1 2019/11/18 19:31:00 martin Exp $ */
+/* $NetBSD: sunxi_dwhdmi.c,v 1.3.6.2 2019/11/25 16:18:40 martin Exp $ */
/*-
* Copyright (c) 2019 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_dwhdmi.c,v 1.3.6.1 2019/11/18 19:31:00 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_dwhdmi.c,v 1.3.6.2 2019/11/25 16:18:40 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -62,6 +62,7 @@
int sc_phandle;
struct fdtbus_phy *sc_phy;
struct fdtbus_regulator *sc_regulator;
+ struct clk *sc_clk;
struct fdt_device_ports sc_ports;
struct drm_display_mode sc_curmode;
@@ -101,13 +102,6 @@
if (encoder == NULL)
return EINVAL;
- sc->sc_phy = fdtbus_phy_get(sc->sc_phandle, "hdmi-phy");
- if (sc->sc_phy == NULL) {
- device_printf(dev, "couldn't find hdmi-phy\n");
- return ENXIO;
- }
-
- sc->sc_regulator = fdtbus_regulator_acquire(sc->sc_phandle, "hvcc-supply");
if (sc->sc_regulator != NULL) {
error = fdtbus_regulator_enable(sc->sc_regulator);
if (error != 0) {
@@ -193,6 +187,15 @@
struct drm_display_mode *adjusted_mode)
{
struct sunxi_dwhdmi_softc * const sc = to_sunxi_dwhdmi_softc(dsc);
+ int error;
+
+ if (sc->sc_clk != NULL) {
+ error = clk_set_rate(sc->sc_clk, adjusted_mode->clock * 1000);
+ if (error != 0)
+ device_printf(sc->sc_base.sc_dev,
+ "couldn't set pixel clock to %u Hz: %d\n",
+ adjusted_mode->clock * 1000, error);
+ }
sc->sc_curmode = *adjusted_mode;
}
@@ -225,20 +228,22 @@
{
struct sunxi_dwhdmi_softc * const sc = device_private(self);
struct fdt_attach_args * const faa = aux;
+ prop_dictionary_t prop = device_properties(self);
const int phandle = faa->faa_phandle;
- struct clk *clk_iahb, *clk_isfr;
+ struct clk *clk_iahb, *clk_isfr, *clk_tmds;
struct fdtbus_reset *rst;
+ bool is_disabled;
bus_addr_t addr;
bus_size_t size;
- if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
- aprint_error(": couldn't get registers\n");
+ if (prop_dictionary_get_bool(prop, "disabled", &is_disabled) && is_disabled) {
+ aprint_naive("\n");
+ aprint_normal(": HDMI TX (disabled)\n");
return;
}
- rst = fdtbus_reset_get(phandle, "ctrl");
- if (rst == NULL || fdtbus_reset_deassert(rst) != 0) {
- aprint_error(": couldn't de-assert reset\n");
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
return;
}
@@ -254,6 +259,12 @@
return;
}
+ clk_tmds = fdtbus_clock_get(phandle, "tmds");
+ if (clk_tmds == NULL || clk_enable(clk_tmds) != 0) {
+ aprint_error(": couldn't enable tmds clock\n");
+ return;
+ }
+
sc->sc_base.sc_dev = self;
sc->sc_base.sc_reg_width = 1;
sc->sc_base.sc_bst = faa->faa_bst;
@@ -265,11 +276,32 @@
sc->sc_base.sc_enable = sunxi_dwhdmi_enable;
sc->sc_base.sc_disable = sunxi_dwhdmi_disable;
sc->sc_base.sc_mode_set = sunxi_dwhdmi_mode_set;
+ sc->sc_base.sc_scl_hcnt = 0xd8;
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