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[src/trunk]: src/sys/arch/arm/nvidia Add Tegra124 APB-DMA controller driver.
details: https://anonhg.NetBSD.org/src/rev/f1e9274ae6bd
branches: trunk
changeset: 823620:f1e9274ae6bd
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Apr 29 11:01:51 2017 +0000
description:
Add Tegra124 APB-DMA controller driver.
diffstat:
sys/arch/arm/nvidia/files.tegra | 7 +-
sys/arch/arm/nvidia/tegra_apbdma.c | 487 ++++++++++++++++++++++++++++++++++
sys/arch/arm/nvidia/tegra_apbdmareg.h | 112 +++++++
3 files changed, 605 insertions(+), 1 deletions(-)
diffs (truncated from 628 to 300 lines):
diff -r c1afe39f93b2 -r f1e9274ae6bd sys/arch/arm/nvidia/files.tegra
--- a/sys/arch/arm/nvidia/files.tegra Sat Apr 29 11:00:56 2017 +0000
+++ b/sys/arch/arm/nvidia/files.tegra Sat Apr 29 11:01:51 2017 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.34 2017/04/28 09:46:49 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.35 2017/04/29 11:01:51 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -67,6 +67,11 @@
attach tegrampio at fdt with tegra_mpio
file arch/arm/nvidia/tegra_mpio.c tegra_mpio
+# APB DMA
+device tegraapbdma
+attach tegraapbdma at fdt with tegra_apbdma
+file arch/arm/nvidia/tegra_apbdma.c tegra_apbdma
+
# XUSB PADCTL
device tegraxusbpad
attach tegraxusbpad at fdt with tegra_xusbpad
diff -r c1afe39f93b2 -r f1e9274ae6bd sys/arch/arm/nvidia/tegra_apbdma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/nvidia/tegra_apbdma.c Sat Apr 29 11:01:51 2017 +0000
@@ -0,0 +1,487 @@
+/* $NetBSD: tegra_apbdma.c,v 1.1 2017/04/29 11:01:51 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_apbdma.c,v 1.1 2017/04/29 11:01:51 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_apbdmareg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#define TEGRA_APBDMA_NCHAN 32
+
+static void * tegra_apbdma_acquire(device_t, const void *, size_t,
+ void (*)(void *), void *);
+static void tegra_apbdma_release(device_t, void *);
+static int tegra_apbdma_transfer(device_t, void *,
+ struct fdtbus_dma_req *);
+static void tegra_apbdma_halt(device_t, void *);
+
+static const struct fdtbus_dma_controller_func tegra_apbdma_funcs = {
+ .acquire = tegra_apbdma_acquire,
+ .release = tegra_apbdma_release,
+ .transfer = tegra_apbdma_transfer,
+ .halt = tegra_apbdma_halt
+};
+
+static int tegra_apbdma_match(device_t, cfdata_t, void *);
+static void tegra_apbdma_attach(device_t, device_t, void *);
+
+static int tegra_apbdma_intr(void *);
+
+struct tegra_apbdma_softc;
+
+struct tegra_apbdma_chan {
+ struct tegra_apbdma_softc *ch_sc;
+ u_int ch_n;
+ void *ch_ih;
+ void (*ch_cb)(void *);
+ void *ch_cbarg;
+};
+
+struct tegra_apbdma_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ int sc_phandle;
+
+ struct tegra_apbdma_chan sc_chan[TEGRA_APBDMA_NCHAN];
+};
+
+CFATTACH_DECL_NEW(tegra_apbdma, sizeof(struct tegra_apbdma_softc),
+ tegra_apbdma_match, tegra_apbdma_attach, NULL, NULL);
+
+#define APBDMA_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define APBDMA_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static int
+tegra_apbdma_match(device_t parent, cfdata_t cf, void *aux)
+{
+ const char * const compatible[] = { "nvidia,tegra124-apbdma", NULL };
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+tegra_apbdma_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_apbdma_softc *sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ struct fdtbus_reset *rst;
+ struct clk *clk;
+ bus_addr_t addr;
+ bus_size_t size;
+ int error;
+ u_int n;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+
+ clk = fdtbus_clock_get_index(phandle, 0);
+ if (clk == NULL) {
+ aprint_error(": couldn't get clock\n");
+ return;
+ }
+ rst = fdtbus_reset_get(phandle, "dma");
+ if (rst == NULL) {
+ aprint_error(": couldn't get reset dma\n");
+ return;
+ }
+
+ fdtbus_reset_assert(rst);
+ error = clk_enable(clk);
+ if (error) {
+ aprint_error(": couldn't enable clock dma: %d\n", error);
+ return;
+ }
+ fdtbus_reset_deassert(rst);
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ sc->sc_phandle = phandle;
+ error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
+ if (error) {
+ aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
+ return;
+ }
+ for (n = 0; n < TEGRA_APBDMA_NCHAN; n++) {
+ sc->sc_chan[n].ch_sc = sc;
+ sc->sc_chan[n].ch_n = n;
+ }
+
+ aprint_naive("\n");
+ aprint_normal(": APBDMA\n");
+
+ /* Stop all channels */
+ for (n = 0; n < TEGRA_APBDMA_NCHAN; n++)
+ APBDMA_WRITE(sc, APBDMACHAN_CSR_REG(n), 0);
+
+ /* Mask interrupts */
+ APBDMA_WRITE(sc, APBDMA_IRQ_MASK_REG, 0);
+
+ /* Global enable */
+ APBDMA_WRITE(sc, APBDMA_COMMAND_REG, APBDMA_COMMAND_GEN);
+
+ fdtbus_register_dma_controller(self, phandle, &tegra_apbdma_funcs);
+}
+
+static int
+tegra_apbdma_intr(void *priv)
+{
+ struct tegra_apbdma_chan *ch = priv;
+ struct tegra_apbdma_softc *sc = ch->ch_sc;
+ const u_int n = ch->ch_n;
+ uint32_t sta;
+
+ sta = APBDMA_READ(sc, APBDMACHAN_STA_REG(n));
+ APBDMA_WRITE(sc, APBDMACHAN_STA_REG(n), sta); /* clear EOC */
+
+ ch->ch_cb(ch->ch_cbarg);
+
+ return 1;
+}
+
+static void *
+tegra_apbdma_acquire(device_t dev, const void *data, size_t len,
+ void (*cb)(void *), void *cbarg)
+{
+ struct tegra_apbdma_softc *sc = device_private(dev);
+ struct tegra_apbdma_chan *ch;
+ char intrstr[128];
+
+ if (len != 1)
+ return NULL;
+
+ const u_int n = be32dec(data);
+ if (n >= TEGRA_APBDMA_NCHAN)
+ return NULL;
+
+ ch = &sc->sc_chan[n];
+ if (ch->ch_ih != NULL) {
+ aprint_error_dev(dev, "dma channel %u is in use\n", n);
+ return NULL;
+ }
+
+ if (!fdtbus_intr_str(sc->sc_phandle, n, intrstr, sizeof(intrstr))) {
+ aprint_error_dev(dev, "failed to decode interrupt %u\n", n);
+ return NULL;
+ }
+
+ ch->ch_ih = fdtbus_intr_establish(sc->sc_phandle, n, IPL_VM,
+ FDT_INTR_MPSAFE, tegra_apbdma_intr, ch);
+ if (ch->ch_ih == NULL) {
+ aprint_error_dev(dev, "failed to establish interrupt on %s\n",
+ intrstr);
+ return NULL;
+ }
+ aprint_normal_dev(dev, "interrupting on %s (channel %u)\n", intrstr, n);
+
+ ch->ch_cb = cb;
+ ch->ch_cbarg = cbarg;
+
+ /* Unmask interrupts for this channel */
+ APBDMA_WRITE(sc, APBDMA_IRQ_MASK_SET_REG, __BIT(n));
+
+ return ch;
+}
+static void
+tegra_apbdma_release(device_t dev, void *priv)
+{
+ struct tegra_apbdma_softc *sc = device_private(dev);
+ struct tegra_apbdma_chan *ch = priv;
+ const u_int n = ch->ch_n;
+
+ KASSERT(ch->ch_ih != NULL);
+
+ /* Halt the channel */
+ APBDMA_WRITE(sc, APBDMACHAN_CSR_REG(n), 0);
+
+ /* Mask interrupts for this channel */
+ APBDMA_WRITE(sc, APBDMA_IRQ_MASK_CLR_REG, __BIT(n));
+
+ fdtbus_intr_disestablish(sc->sc_phandle, ch->ch_ih);
+
+ ch->ch_cb = NULL;
+ ch->ch_cbarg = NULL;
+}
+
+static int
+tegra_apbdma_transfer(device_t dev, void *priv, struct fdtbus_dma_req *req)
+
+{
+ struct tegra_apbdma_softc *sc = device_private(dev);
+ struct tegra_apbdma_chan *ch = priv;
+ const u_int n = ch->ch_n;
+ uint32_t csr = 0;
+ uint32_t csre = 0;
+ uint32_t ahb_seq = 0;
+ uint32_t apb_seq = 0;
+
+ /* Scatter-gather not supported */
+ if (req->dreq_nsegs != 1)
+ return EINVAL;
+
+ /* Addresses must be aligned to 32-bits */
+ if ((req->dreq_segs[0].ds_addr & 3) != 0 ||
+ (req->dreq_dev_phys & 3) != 0)
+ return EINVAL;
+
+ /* Length must be a multiple of 32-bits */
+ if ((req->dreq_segs[0].ds_len & 3) != 0)
+ return EINVAL;
+
+ /* REQ_SEL is between 0 and 31 */
+ if (req->dreq_sel < 0 || req->dreq_sel > 31)
+ return EINVAL;
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