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[src/netbsd-7]: src Pull up following revision(s) (requested by msaitoh in ti...
details: https://anonhg.NetBSD.org/src/rev/84cf2b0b9128
branches: netbsd-7
changeset: 800541:84cf2b0b9128
user: snj <snj%NetBSD.org@localhost>
date: Tue Oct 09 15:43:38 2018 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #1636):
sys/arch/x86/include/cacheinfo.h: 1.23-1.26
sys/arch/x86/include/cpu.h: 1.70
sys/arch/x86/include/specialreg.h: 1.91-1.93,1.98,1.100,1.102-1.124,1.126,1.130 via patch
sys/arch/x86/x86/cpu_topology.c: 1.10
sys/arch/x86/x86/identcpu.c: 1.56-1.57,1.70 via patch
usr.sbin/cpuctl/arch/i386.c: 1.71,1.75-1.79,1.81-1.85 via patch
Add some register definitions for x86:
- Add CLWB bit.
- Fix a few (unused) MSR values, and add some bit definitions of
MSR_EFER from Murray Armfield in PR#42861.
- CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify
comments and snprintb() string.
- Define CPUID Fn00000001 %ebx bits and use them.
No functional change.
- Add Structured Extended Flags Enumeration Leaf's bit definitions:
AVX512_{IFMA,VBMI2,VNNI,BITALG,VPOPCNTDQ,4VNNIW,4FMAPS},GFNI&VAES.
- Add Turbo Boost Max Technology 3.0 bit.
- Add AMD SVM features definitions.
- Add Intel cpuid 7 %edx IBRS and STIBP bit definitions.
- Fix swapped comments for EFER LME and LMA
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add MSR_IA32_ARCH_CAPABILITIES definition.
- Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
- Add Intel Deterministic Address Translation Parameter Leaf(0x18)
definitions.
- s/CLFUSH/CLFLUSH/
- Add AMD's Disable Indirect Branch Predictor bit definition.
- Add the MSR bits definitions for IBRS, STIBP and IBPB.
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
- Add AMD's CPUID Fn80000001 %edx MMX and FXSR bit definitions.
- Add RDCL_NO and IBRS_ALL.
- Add SSBD and RSBA bit definitions.
- Add AMD's SSB bit definitions for F15H, F16H and F17H.
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.
- Add yet another Shared L2 TLB (2M/4M pages).
- Add 3way and 6way of L2 cache or TLB on AMD CPU.
- AMD L3 cache association bitfield is not 8bit but 4bit like others
association bitfields.
- Sort entries. No functional change.
- Modify comment, fix typo in comment and add comment.
cpuctl(8):
- Add detection for Quark X1000, Xeon E5 v4, E7 v4,
Core i7-69xx Extreme Edition, Xeon Scalable (Skylake),
Xeon Phi [357]200 (Knights Landing), Atom (Goldmont),
Atom (Denverton), Future Core (Cannon Lake), Atom (Goldmont Plus),
Xeon Phi 7215, 7285 and 7295 (Knights Mill) and
7th or 8th gen Core (Kaby Lake, Coffee Lake).
- Print Structured Extended Feature leaf Fn0000_0007 %ebx on AMD,too.
- Print Fn0000_0007 %ecx on Intel.
- Print Intel cpuid 7 %edx.
- Parse the TLB info from `cpuid leaf 18H' on Intel processor.
- Use aprint_error_dev() for error output.
diffstat:
sys/arch/x86/include/cacheinfo.h | 12 +-
sys/arch/x86/include/cpu.h | 4 +-
sys/arch/x86/include/specialreg.h | 231 ++++++++++++++++++++++++---------
sys/arch/x86/x86/cpu_topology.c | 6 +-
sys/arch/x86/x86/identcpu.c | 9 +-
usr.sbin/cpuctl/arch/i386.c | 253 ++++++++++++++++++++++++++++++-------
6 files changed, 389 insertions(+), 126 deletions(-)
diffs (truncated from 974 to 300 lines):
diff -r 09b620dd456a -r 84cf2b0b9128 sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h Wed Aug 29 17:04:45 2018 +0000
+++ b/sys/arch/x86/include/cacheinfo.h Tue Oct 09 15:43:38 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.18.2.3 2016/12/08 00:15:25 snj Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.18.2.4 2018/10/09 15:43:38 snj Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -35,9 +35,10 @@
#define CAI_L2_DTLB2 15 /* L2 Data TLB (2/4M pages) */
#define CAI_L2_STLB 16 /* Shared L2 TLB (4K pages) */
#define CAI_L2_STLB2 17 /* Shared L2 TLB (4K/2M pages) */
-#define CAI_PREFETCH 18 /* Prefetch */
+#define CAI_L2_STLB3 18 /* Shared L2 TLB (2M/4M pages) */
+#define CAI_PREFETCH 19 /* Prefetch */
-#define CAI_COUNT 19
+#define CAI_COUNT 20
/*
* AMD Cache Info:
@@ -139,7 +140,7 @@
/* L3 Cache */
#define AMD_L3_EDX_C_SIZE(x) ((((x) >> 18) & 0xffff) * 1024 * 512)
-#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xff)
+#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xf)
#define AMD_L3_EDX_C_LPT(x) (((x) >> 8) & 0xf)
#define AMD_L3_EDX_C_LS(x) ( (x) & 0xff)
@@ -333,6 +334,7 @@
__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_PREFETCH, 0xf0, 0, 0, 64, NULL), \
__CI_TBL(CAI_PREFETCH, 0xf1, 0, 0,128, NULL), \
+/* 0xfe means no TLB information in CPUID leaf 2 (and use leaf 0x18) */ \
/* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
__CI_TBL(0, 0, 0, 0, 0, NULL) \
}
@@ -340,7 +342,9 @@
#define AMD_L2CACHE_INFO { \
__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
+__CI_TBL(0, 0x03, 3, 0, 0, NULL), \
__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
+__CI_TBL(0, 0x05, 6, 0, 0, NULL), \
__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
diff -r 09b620dd456a -r 84cf2b0b9128 sys/arch/x86/include/cpu.h
--- a/sys/arch/x86/include/cpu.h Wed Aug 29 17:04:45 2018 +0000
+++ b/sys/arch/x86/include/cpu.h Tue Oct 09 15:43:38 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.66.4.1 2016/03/06 17:53:26 martin Exp $ */
+/* $NetBSD: cpu.h,v 1.66.4.2 2018/10/09 15:43:38 snj Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -170,7 +170,7 @@
const struct cpu_functions *ci_func; /* start/stop functions */
struct trapframe *ci_ddb_regs;
- u_int ci_cflush_lsize; /* CFLUSH insn line size */
+ u_int ci_cflush_lsize; /* CLFLUSH insn line size */
struct x86_cache_info ci_cinfo[CAI_COUNT];
union descriptor *ci_gdt;
diff -r 09b620dd456a -r 84cf2b0b9128 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Wed Aug 29 17:04:45 2018 +0000
+++ b/sys/arch/x86/include/specialreg.h Tue Oct 09 15:43:38 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.78.4.5 2016/12/08 00:15:25 snj Exp $ */
+/* $NetBSD: specialreg.h,v 1.78.4.6 2018/10/09 15:43:38 snj Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -128,7 +128,7 @@
#define CPUID_DE 0x00000004 /* has debugging extension */
#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
#define CPUID_TSC 0x00000010 /* has time stamp counter */
-#define CPUID_MSR 0x00000020 /* has mode specific registers */
+#define CPUID_MSR 0x00000020 /* has model specific registers */
#define CPUID_PAE 0x00000040 /* has phys address extension */
#define CPUID_MCE 0x00000080 /* has machine check exception */
#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
@@ -142,7 +142,7 @@
#define CPUID_PAT 0x00010000 /* Page Attribute Table */
#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
#define CPUID_PN 0x00040000 /* processor serial number */
-#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
+#define CPUID_CFLUSH 0x00080000 /* CLFLUSH insn supported */
#define CPUID_B20 0x00100000 /* reserved */
#define CPUID_DS 0x00200000 /* Debug Store */
#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
@@ -161,7 +161,7 @@
"\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
"\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
"\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
- "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \
+ "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \
"\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
"\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
"\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF"
@@ -246,6 +246,12 @@
&& (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \
? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
+/* CPUID Fn00000001 %ebx */
+#define CPUID_BRAND_INDEX __BITS(7,0)
+#define CPUID_CLFLUSH_SIZE __BITS(15,8)
+#define CPUID_HTT_CORES __BITS(23,16)
+#define CPUID_LOCAL_APIC_ID __BITS(31,24)
+
/*
* Intel Deterministic Cache Parameter Leaf
* Fn0000_0004
@@ -290,13 +296,21 @@
#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */
#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */
#define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */
-#define CPUID_DSPM_HDC __BIT(13) /* HDC */
+#define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */
+#define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */
+#define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */
+#define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */
+#define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */
+#define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */
+#define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */
#define CPUID_DSPM_FLAGS "\20" \
"\1" "DTS" "\2" "IDA" "\3" "ARAT" \
"\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \
"\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \
- "\16" "HDC"
+ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \
+ "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \
+ "25" "HWP_IGNIDL"
/*
* Intel Digital Thermal Sensor and
@@ -313,38 +327,41 @@
* %eax: The Maximun input value for supported subleaf.
* %ebx: Feature bits.
* %ecx: Feature bits.
+ * %edx: Feature bits.
*/
/* %ebx */
-#define CPUID_SEF_FSGSBASE __BIT(0)
-#define CPUID_SEF_TSC_ADJUST __BIT(1)
-#define CPUID_SEF_SGX __BIT(2)
-#define CPUID_SEF_BMI1 __BIT(3)
-#define CPUID_SEF_HLE __BIT(4)
-#define CPUID_SEF_AVX2 __BIT(5)
-#define CPUID_SEF_FDPEXONLY __BIT(6)
-#define CPUID_SEF_SMEP __BIT(7)
-#define CPUID_SEF_BMI2 __BIT(8)
-#define CPUID_SEF_ERMS __BIT(9)
-#define CPUID_SEF_INVPCID __BIT(10)
-#define CPUID_SEF_RTM __BIT(11)
-#define CPUID_SEF_QM __BIT(12)
-#define CPUID_SEF_FPUCSDS __BIT(13)
-#define CPUID_SEF_MPX __BIT(14)
-#define CPUID_SEF_PQE __BIT(15)
-#define CPUID_SEF_AVX512F __BIT(16)
-#define CPUID_SEF_AVX512DQ __BIT(17)
-#define CPUID_SEF_RDSEED __BIT(18)
-#define CPUID_SEF_ADX __BIT(19)
-#define CPUID_SEF_SMAP __BIT(20)
-#define CPUID_SEF_CLFLUSHOPT __BIT(23)
-#define CPUID_SEF_PT __BIT(25)
-#define CPUID_SEF_AVX512PF __BIT(26)
-#define CPUID_SEF_AVX512ER __BIT(27)
-#define CPUID_SEF_AVX512CD __BIT(28)
-#define CPUID_SEF_SHA __BIT(29)
-#define CPUID_SEF_AVX512BW __BIT(30)
-#define CPUID_SEF_AVX512VL __BIT(31)
+#define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */
+#define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */
+#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extentions */
+#define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */
+#define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */
+#define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */
+#define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */
+#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Excecution Prevention */
+#define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */
+#define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */
+#define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */
+#define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */
+#define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */
+#define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */
+#define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */
+#define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */
+#define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */
+#define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */
+#define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */
+#define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */
+#define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */
+#define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */
+#define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */
+#define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */
+#define CPUID_SEF_PT __BIT(25) /* Processor Trace */
+#define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */
+#define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */
+#define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */
+#define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */
+#define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */
+#define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */
#define CPUID_SEF_FLAGS "\20" \
"\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \
@@ -352,24 +369,48 @@
"\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
"\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
"\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
- "\25" "SMAP" "\30" "CLFLUSHOPT" \
- "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
+ "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \
+ "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
"\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
/* %ecx */
-#define CPUID_SEF_PREFETCHWT1 __BIT(0)
-#define CPUID_SEF_UMIP __BIT(2)
-#define CPUID_SEF_PKU __BIT(3)
-#define CPUID_SEF_OSPKE __BIT(4)
-#define CPUID_SEF_RDPID __BIT(22)
-#define CPUID_SEF_SGXLC __BIT(30)
+#define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */
+#define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */
+#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */
+#define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */
+#define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */
+#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
+#define CPUID_SEF_GFNI __BIT(8)
+#define CPUID_SEF_VAES __BIT(9)
+#define CPUID_SEF_VPCLMULQDQ __BIT(10)
+#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */
+#define CPUID_SEF_AVX512_BITALG __BIT(12)
+#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
+#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
+#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
#define CPUID_SEF_FLAGS1 "\20" \
- "\1" "PREFETCHWT1" "\3" "UMIP" "\4" "PKU" \
- "\5" "OSPKE" \
+ "\1" "PREFETCHWT1" "\2" "AVX512_VBMI" "\3" "UMIP" "\4" "PKU" \
+ "\5" "OSPKE" "\7" "AVX512_VBMI2" \
+ "\11" "GFNI" "\12" "VAES" "\13" "VPCLMULQDQ" "\14" "AVX512_VNNI"\
+ "\15" "AVX512_BITALG" "\17" "AVX512_VPOPCNTDQ" \
"\27" "RDPID" \
"\37" "SGXLC"
+/* %edx */
+#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
+#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
+#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
+#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
+#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */
+#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
+#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
+
+#define CPUID_SEF_FLAGS2 "\20" \
+ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
+ "\33" "IBRS" "\34" "STIBP" \
+ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD"
+
/*
* CPUID Processor extended state Enumeration Fn0000000d
*
@@ -401,6 +442,35 @@
#define CPUID_PES1_FLAGS "\20" \
"\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES"
+/*
+ * Intel Deterministic Address Translation Parameter Leaf
+ * Fn0000_0018
+ */
+
+/* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */
+
+/* %ebx */
+#define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */
+#define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */
+#define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */
+#define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */
+#define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */
+#define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */
+#define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */
+
+/* Number of sets: %ecx */
+
+/* %edx */
+#define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */
+#define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */
+#define CPUID_DATP_TCTYPE_D 1 /* Data TLB */
+#define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */
+#define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */
+#define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */
+#define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */
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