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[src/trunk]: src/sys Add support for I2C designware controllers (as found in ...
details: https://anonhg.NetBSD.org/src/rev/e6413f6a35ce
branches: trunk
changeset: 828383:e6413f6a35ce
user: bouyer <bouyer%NetBSD.org@localhost>
date: Sun Dec 10 17:12:54 2017 +0000
description:
Add support for I2C designware controllers (as found in Intel PCH devices),
with a pci front-end.
The pci front-end is tied to ACPI and Intel-specific, so it's in arch/x86/pci
and not dev/pci.
Core driver from OpenBSD, PCI front-end by me.
diffstat:
sys/arch/x86/pci/dwiic_pci.c | 213 ++++++++++++++
sys/arch/x86/pci/files.pci | 5 +-
sys/arch/x86/pci/lpssreg.h | 92 ++++++
sys/conf/files | 7 +-
sys/dev/ic/dwiic.c | 623 +++++++++++++++++++++++++++++++++++++++++++
sys/dev/ic/dwiic_var.h | 80 +++++
6 files changed, 1018 insertions(+), 2 deletions(-)
diffs (truncated from 1064 to 300 lines):
diff -r e81840c51c03 -r e6413f6a35ce sys/arch/x86/pci/dwiic_pci.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/x86/pci/dwiic_pci.c Sun Dec 10 17:12:54 2017 +0000
@@ -0,0 +1,213 @@
+/* $NetBSD: dwiic_pci.c,v 1.1 2017/12/10 17:12:54 bouyer Exp $ */
+
+/*-
+ * Copyright (c) 2017 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Synopsys DesignWare I2C controller, PCI front-end
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: dwiic_pci.c,v 1.1 2017/12/10 17:12:54 bouyer Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/acpi/acpivar.h>
+#include <dev/acpi/acpi_pci.h>
+#include <dev/acpi/acpi_util.h>
+#include <dev/acpi/acpi_i2c.h>
+
+#include <dev/ic/dwiic_var.h>
+#include <arch/x86/pci/lpssreg.h>
+
+//#define DWIIC_DEBUG
+
+#ifdef DWIIC_DEBUG
+#define DPRINTF(x) printf x
+#else
+#define DPRINTF(x)
+#endif
+
+struct pci_dwiic_softc {
+ struct dwiic_softc sc_dwiic;
+ pci_chipset_tag_t sc_pc;
+ pcitag_t sc_ptag;
+ struct acpi_devnode *sc_acpinode;
+};
+
+static uint32_t
+lpss_read(struct pci_dwiic_softc *sc, int offset)
+{
+ u_int32_t b = bus_space_read_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh,
+ offset);
+ return b;
+}
+
+static void
+lpss_write(struct pci_dwiic_softc *sc, int offset, uint32_t val)
+{
+ bus_space_write_4(sc->sc_dwiic.sc_iot, sc->sc_dwiic.sc_ioh,
+ offset, val);
+}
+
+static int pci_dwiic_match(device_t, cfdata_t, void *);
+static void pci_dwiic_attach(device_t, device_t, void *);
+static bool dwiic_pci_power(struct dwiic_softc *, bool);
+
+CFATTACH_DECL_NEW(pcidwiic, sizeof(struct pci_dwiic_softc),
+ pci_dwiic_match, pci_dwiic_attach, dwiic_detach, NULL);
+
+
+int
+pci_dwiic_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+
+ if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
+ return 0;
+
+ if (PCI_PRODUCT(pa->pa_id) < PCI_PRODUCT_INTEL_100SERIES_LP_I2C_0 ||
+ PCI_PRODUCT(pa->pa_id) > PCI_PRODUCT_INTEL_100SERIES_LP_I2C_3)
+ return 0;
+
+ return 1;
+}
+
+void
+pci_dwiic_attach(device_t parent, device_t self, void *aux)
+{
+ struct pci_dwiic_softc *sc = device_private(self);
+ struct pci_attach_args *pa = aux;
+ const char *intrstr;
+ pci_intr_handle_t intrhandle;
+ char intrbuf[PCI_INTRSTR_LEN];
+ pcireg_t memtype;
+ pcireg_t csr;
+ uint32_t caps;
+
+ sc->sc_dwiic.sc_dev = self;
+ sc->sc_dwiic.sc_power = dwiic_pci_power;
+ sc->sc_dwiic.sc_type = dwiic_type_sunrisepoint;
+
+ sc->sc_pc = pa->pa_pc;
+ sc->sc_ptag = pa->pa_tag;
+
+ /* register access not enabled by BIOS */
+ csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+ pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
+ csr | PCI_COMMAND_MEM_ENABLE);
+
+ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR0);
+ if (pci_mapreg_map(pa, PCI_BAR0, memtype, 0, &sc->sc_dwiic.sc_iot,
+ &sc->sc_dwiic.sc_ioh, NULL, NULL) != 0) {
+ aprint_error(": can't map register space\n");
+ goto out;
+ }
+ dwiic_pci_power(&sc->sc_dwiic, 1);
+
+ caps = lpss_read(sc, LPSS_CAP);
+
+ aprint_naive(": I2C controller\n");
+ aprint_normal(": I2C controller instance %d\n",
+ (int)(caps & LPSS_CAP_INSTANCE));
+
+ if (pci_intr_map(pa, &intrhandle)) {
+ aprint_error_dev(self, "can't map interrupt\n");
+ goto out;
+ }
+ intrstr = pci_intr_string(pa->pa_pc, intrhandle,
+ intrbuf, sizeof(intrbuf));
+
+ sc->sc_dwiic.sc_ih = pci_intr_establish(pa->pa_pc, intrhandle,
+ IPL_VM, dwiic_intr, sc);
+ if (sc->sc_dwiic.sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt");
+ if (intrstr != NULL)
+ aprint_error(" at %s", intrstr);
+ aprint_error("\n");
+ goto out;
+ }
+ aprint_normal_dev(self, "interrupting at %s\n", intrstr);
+
+ lpss_write(sc, LPSS_RESET, LPSS_RESET_CTRL_REL);
+ lpss_write(sc, LPSS_REMAP_LO,
+ pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0));
+ lpss_write(sc, LPSS_REMAP_HI,
+ pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_BAR0 + 0x4));
+
+ sc->sc_acpinode = acpi_pcidev_find(0 /*XXX segment*/,
+ pa->pa_bus, pa->pa_device, pa->pa_function);
+
+ if (sc->sc_acpinode) {
+ sc->sc_dwiic.sc_iba.iba_child_devices =
+ acpi_enter_i2c_devs(sc->sc_acpinode);
+ } else {
+ aprint_verbose_dev(self, "no matching ACPI node\n");
+ }
+
+ dwiic_attach(&sc->sc_dwiic);
+
+ pmf_device_register(self, dwiic_suspend, dwiic_resume);
+
+out:
+ return;
+}
+
+static bool
+dwiic_pci_power(struct dwiic_softc *dwsc, bool power)
+{
+ struct pci_dwiic_softc *sc = (void *)dwsc;
+ pcireg_t pmreg;
+
+ printf("status 0x%x\n", pci_conf_read(sc->sc_pc, sc->sc_ptag, PCI_COMMAND_STATUS_REG));
+ printf("reset 0x%x\n", lpss_read(sc, LPSS_RESET));
+ printf("rlo 0x%x\n", lpss_read(sc, LPSS_REMAP_LO));
+ printf("rho 0x%x\n", lpss_read(sc, LPSS_REMAP_HI));
+
+ if (!power)
+ lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_OFF);
+ if (pci_get_capability(sc->sc_pc, sc->sc_ptag, PCI_CAP_PWRMGMT,
+ &pmreg, NULL)) {
+ DPRINTF(("%s: power status 0x%x", device_xname(dwsc->sc_dev),
+ pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR)));
+ pci_conf_write(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR,
+ power ? PCI_PMCSR_STATE_D0 : PCI_PMCSR_STATE_D3);
+ DELAY(10000); /* 10 milliseconds */
+ DPRINTF((" -> 0x%x\n",
+ pci_conf_read(sc->sc_pc, sc->sc_ptag, pmreg + PCI_PMCSR)));
+ }
+ if (power) {
+ lpss_write(sc, LPSS_CLKGATE, LPSS_CLKGATE_CTRL_ON);
+ }
+ return true;
+}
diff -r e81840c51c03 -r e6413f6a35ce sys/arch/x86/pci/files.pci
--- a/sys/arch/x86/pci/files.pci Sun Dec 10 17:05:54 2017 +0000
+++ b/sys/arch/x86/pci/files.pci Sun Dec 10 17:12:54 2017 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.pci,v 1.20 2015/05/03 02:50:59 pgoyette Exp $
+# $NetBSD: files.pci,v 1.21 2017/12/10 17:12:54 bouyer Exp $
device aapic
attach aapic at pci
@@ -39,6 +39,9 @@
attach amdtemp at amdnb_miscbus
file arch/x86/pci/amdtemp.c amdtemp
+attach dwiic at pci with pcidwiic
+file arch/x86/pci/dwiic_pci.c pcidwiic
+
# PCI-LPC bridges
device rdcpcib: isabus, sysmon_wdog
attach rdcpcib at pci
diff -r e81840c51c03 -r e6413f6a35ce sys/arch/x86/pci/lpssreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/x86/pci/lpssreg.h Sun Dec 10 17:12:54 2017 +0000
@@ -0,0 +1,92 @@
+/* $NetBSD: lpssreg.h,v 1.1 2017/12/10 17:12:54 bouyer Exp $ */
+
+/*-
+ * Copyright (c) 2017 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* LPSS registers, as found in several functions of Ivy Lake bridge */
+#define LPSS_RESET 0x204
+#define LPSS_RESET_DMA __BIT(2)
+#define LPSS_RESET_CTRL __BITS(1,0)
+#define LPSS_RESET_CTRL_ASSERT 0
+#define LPSS_RESET_CTRL_REL 0x3
+
+#define LPSS_ACTIVELTR 0x210
+#define LPSS_ACTIVELTR_SSCALE __BITS(12,10)
+#define LPSS_ACTIVELTR_SSCALE_1 (0x2 << 10)
+#define LPSS_ACTIVELTR_SSCALE_32 (0x3 << 10)
+#define LPSS_ACTIVELTR_SVALUE __BITS(9,0)
+
+#define LPSS_IDLELTR 0x214
+#define LPSS_IDLELTR_SSCALE __BITS(12,10)
+#define LPSS_IDLELTR_SSCALE_1 (0x2 << 10)
+#define LPSS_IDLELTR_SSCALE_32 (0x3 << 10)
+#define LPSS_IDLELTR_SVALUE __BITS(9,0)
+
+#define LPSS_TXACK 0x218
+#define LPSS_TXACK_OVF __BIT(31)
+#define LPSS_TXACK_CNT __BITS(23,0)
+
+#define LPSS_RXACK 0x21C
+#define LPSS_RXACK_OVF __BIT(31)
+#define LPSS_RXACK_CNT __BITS(23,0)
+
+#define LPSS_TX_IRQ 0x220
+#define LPSS_TX_IRQ_MSK __BIT(1)
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