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[src/netbsd-7]: src/sys/arch Pull up following revision(s) (requested by skrl...
details: https://anonhg.NetBSD.org/src/rev/0b9aaff0a79d
branches: netbsd-7
changeset: 800155:0b9aaff0a79d
user: snj <snj%NetBSD.org@localhost>
date: Sat Mar 11 07:40:21 2017 +0000
description:
Pull up following revision(s) (requested by skrll in ticket #1366):
sys/arch/arm/include/arm32/pmap.h: 1.145
sys/arch/arm/arm32/pmap.c: 1.343, 1.344
sys/arch/evbarm/gumstix/gumstix_machdep.c: 1.58 via patch
Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and
fix the options for xscale boards which require the code in
pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC.
Fix the typo (pte -> opte) in this code block and consistently use opte
elsewhere.
PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5 on copyout in init
--
fix unused.
--
Set xscale_cache_clean_addr appropriately and re-arrange default KVA
layout to allow direct map for all boards.
OVERO/DUOVERO/PEPPER aren't tested.
PR/52010: Regression: Gumstix Verdex is hanging in enabling cache + KASSERT ram_size
diffstat:
sys/arch/arm/arm32/pmap.c | 18 +++++++++---------
sys/arch/arm/include/arm32/pmap.h | 18 ++++++++++++------
sys/arch/evbarm/gumstix/gumstix_machdep.c | 16 +++++++++++-----
3 files changed, 32 insertions(+), 20 deletions(-)
diffs (151 lines):
diff -r 82c88a588442 -r 0b9aaff0a79d sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Thu Mar 09 16:28:13 2017 +0000
+++ b/sys/arch/arm/arm32/pmap.c Sat Mar 11 07:40:21 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.295.2.8 2016/02/26 22:31:06 snj Exp $ */
+/* $NetBSD: pmap.c,v 1.295.2.9 2017/03/11 07:40:21 snj Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -217,7 +217,7 @@
#include <arm/locore.h>
//#include <arm/arm32/katelib.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.295.2.8 2016/02/26 22:31:06 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.295.2.9 2017/03/11 07:40:21 snj Exp $");
//#define PMAP_DEBUG
#ifdef PMAP_DEBUG
@@ -968,6 +968,7 @@
* - The specified pmap is 'active' in the cache/tlb.
*/
+#ifdef PMAP_INCLUDE_PTE_SYNC
static inline void
pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep)
{
@@ -976,10 +977,9 @@
arm_dsb();
}
-#ifdef PMAP_INCLUDE_PTE_SYNC
-#define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep)
+# define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep)
#else
-#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
+# define PTE_SYNC_CURRENT(pm, ptep) __nothing
#endif
/*
@@ -1708,7 +1708,7 @@
/*
* Page tables must have the cache-mode set correctly.
*/
- const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK)
+ const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK)
| pte_l2_s_cache_mode_pt;
l2pte_set(ptep, npte, opte);
PTE_SYNC(ptep);
@@ -1987,7 +1987,7 @@
pt_entry_t npte = opte & ~L2_S_CACHE_MASK;
if ((va != pv->pv_va || pm != pv->pv_pmap)
- && l2pte_valid_p(npte)) {
+ && l2pte_valid_p(opte)) {
#ifdef PMAP_CACHE_VIVT
pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va,
true, pv->pv_flags);
@@ -2315,7 +2315,7 @@
if (opte == npte) /* only update is there's a change */
continue;
- if (l2pte_valid_p(npte)) {
+ if (l2pte_valid_p(opte)) {
pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags);
}
@@ -4252,7 +4252,7 @@
if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0)
goto out;
- paddr_t pa = l2pte_pa(pte);
+ paddr_t pa = l2pte_pa(opte);
struct vm_page * const pg = PHYS_TO_VM_PAGE(pa);
KASSERT(pg != NULL);
diff -r 82c88a588442 -r 0b9aaff0a79d sys/arch/arm/include/arm32/pmap.h
--- a/sys/arch/arm/include/arm32/pmap.h Thu Mar 09 16:28:13 2017 +0000
+++ b/sys/arch/arm/include/arm32/pmap.h Sat Mar 11 07:40:21 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.135.2.2 2015/05/27 05:33:29 msaitoh Exp $ */
+/* $NetBSD: pmap.h,v 1.135.2.3 2017/03/11 07:40:21 snj Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -479,15 +479,21 @@
extern int pmap_needs_pte_sync;
#if defined(_KERNEL_OPT)
/*
+ * Perform compile time evaluation of PMAP_NEEDS_PTE_SYNC when only a
+ * single MMU type is selected.
+ *
* StrongARM SA-1 caches do not have a write-through mode. So, on these,
- * we need to do PTE syncs. If only SA-1 is configured, then evaluate
- * this at compile time.
+ * we need to do PTE syncs. Additionally, V6 MMUs also need PTE syncs.
+ * Finally, MEMC, GENERIC and XSCALE MMUs do not need PTE syncs.
+ *
+ * Use run time evaluation for all other cases.
+ *
*/
-#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1)
+#if (ARM_NMMUS == 1)
+#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0)
#define PMAP_INCLUDE_PTE_SYNC
-#if (ARM_MMU_V6 > 0)
#define PMAP_NEEDS_PTE_SYNC 1
-#elif (ARM_MMU_SA1 == 0)
+#elif (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_XSCALE != 0)
#define PMAP_NEEDS_PTE_SYNC 0
#endif
#endif
diff -r 82c88a588442 -r 0b9aaff0a79d sys/arch/evbarm/gumstix/gumstix_machdep.c
--- a/sys/arch/evbarm/gumstix/gumstix_machdep.c Thu Mar 09 16:28:13 2017 +0000
+++ b/sys/arch/evbarm/gumstix/gumstix_machdep.c Sat Mar 11 07:40:21 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gumstix_machdep.c,v 1.50 2014/06/07 10:30:13 kiyohara Exp $ */
+/* $NetBSD: gumstix_machdep.c,v 1.50.2.1 2017/03/11 07:40:21 snj Exp $ */
/*
* Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation.
* All rights reserved.
@@ -187,13 +187,16 @@
#endif
/*
- * The range 0xc1000000 - 0xcfffffff is available for kernel VM space
- * Core-logic registers and I/O mappings occupy 0xfd000000 - 0xffffffff
+ * The range 0xc1000000 - 0xfd000000 is available for kernel VM space
+ * Core-logic registers and I/O mappings occupy
+ *
+ * 0xfd000000 - 0xfd800000 on gumstix
+ * 0xc0000000 - 0xc0400000 on overo, duovero and pepper
*/
#ifndef KERNEL_VM_BASE
-#define KERNEL_VM_BASE 0xc1000000
+#define KERNEL_VM_BASE 0xc8000000
#endif
-#define KERNEL_VM_SIZE 0x0f000000
+#define KERNEL_VM_SIZE 0x35000000
BootConfig bootconfig; /* Boot config storage */
static char bootargs[MAX_BOOT_STRING];
@@ -397,6 +400,9 @@
*/
#if defined(GUMSTIX)
+ extern vaddr_t xscale_cache_clean_addr;
+ xscale_cache_clean_addr = 0xff000000U;
+
cpu_reset_address = NULL;
#elif defined(OVERO)
cpu_reset_address = overo_reset;
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