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[src/trunk]: src/sys/arch/powerpc/include/booke Added some register definitio...
details: https://anonhg.NetBSD.org/src/rev/7f344e1611eb
branches: trunk
changeset: 806477:7f344e1611eb
user: nonaka <nonaka%NetBSD.org@localhost>
date: Thu Feb 26 02:27:40 2015 +0000
description:
Added some register definitions for multi-queue.
diffstat:
sys/arch/powerpc/include/booke/etsecreg.h | 115 +++++++++++++++++++++++++++--
1 files changed, 106 insertions(+), 9 deletions(-)
diffs (199 lines):
diff -r 93e7371ac8e3 -r 7f344e1611eb sys/arch/powerpc/include/booke/etsecreg.h
--- a/sys/arch/powerpc/include/booke/etsecreg.h Thu Feb 26 02:21:38 2015 +0000
+++ b/sys/arch/powerpc/include/booke/etsecreg.h Thu Feb 26 02:27:40 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: etsecreg.h,v 1.7 2015/02/26 02:21:38 nonaka Exp $ */
+/* $NetBSD: etsecreg.h,v 1.8 2015/02/26 02:27:40 nonaka Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -109,15 +109,16 @@
#define RXFCB_CTU 0x0400 /* TCP or UDP checksum checked */
#define RXFCB_EIP 0x0200 /* IPv4 header checksum error */
#define RXFCB_ETU 0x0100 /* TCP or UDP header checksum error */
+#define RXFCB_HASH_VAL 0x0010 /* FLR_HASH value is valid */
#define RXFCB_PERR 0x000c /* Parse Error */
#define RXFCB_PERR_L3 0x0008 /* L3 Parse Error */
struct rxfcb {
uint16_t rxfcb_flags;
- uint8_t rxfcb_rq; /* receive queue index */
- uint8_t rxfcb_pro; /* IP Protocol received */
- uint16_t rxfcb__mbz1;
- uint16_t rxfcb_vlctl; /* VLAN control field */
+ uint8_t rxfcb_rq; /* receive queue index */
+ uint8_t rxfcb_pro; /* IP Protocol received */
+ uint16_t rxfcb_flr_hash; /* filer hash value */
+ uint16_t rxfcb_vlctl; /* VLAN control field */
};
/* 0x000-0x0ff eTSEC general control/status registers */
@@ -139,7 +140,8 @@
#define IEVENT_CRL __PPCBIT(14) /* collision retry limit */
#define IEVENT_XFUN __PPCBIT(15) /* transmit fifo underrun */
#define IEVENT_RXB __PPCBIT(16) /* receive buffer */
-#define IEVENT_MAG __PPCBIT(29) /* magic packet detected */
+#define IEVENT_TWK __PPCBIT(19) /* timer wakeup */
+#define IEVENT_MAG __PPCBIT(20) /* magic packet detected */
#define IEVENT_MMRD __PPCBIT(21) /* MMI manangement read complete */
#define IEVENT_MMWR __PPCBIT(22) /* MMI manangement write complete */
#define IEVENT_GRSC __PPCBIT(23) /* graceful receive stop complete */
@@ -188,7 +190,10 @@
#define TCTRL_THDF __PPCBIT(29) /* Transmit half duplex */
#define TCTRL_RFC_PAUSE __PPCBIT(27) /* receive flow control pause frame */
#define TCTRL_TFC_PAUSE __PPCBIT(28) /* transmit flow control pause frame */
-#define TXSCHED __PPCBITS(29,30) /* transmit ring scheduling algorithm */
+#define TCTRL_TXSCHED __PPCBITS(29,30) /* transmit ring scheduling algorithm */
+#define TCTRL_TXSCHED_SINGLE __SHIFTIN(0,TCTRL_TXSCHED)
+#define TCTRL_TXSCHED_PRIO __SHIFTIN(1,TCTRL_TXSCHED)
+#define TCTRL_TXSCHED_MWRR __SHIFTIN(2,TCTRL_TXSCHED)
#define TSTAT 0x104 /* Transmit status register */
#define TSTAT_THLT0 __PPCBIT(0) /* transmit halt of ring 0 */
@@ -264,6 +269,10 @@
/* 0x300-0x4ff eTSEC receive control/status registers */
#define RCTRL 0x300 /* Receive control register */
+#define RCTRL_L2OFF __PPCBITS(0,6)
+#define RCTRL_L2OFF_SET(n) __SHIFTIN((n),RCTRL_L2OFF)
+#define RCTRL_TS __PPCBIT(7)
+#define RCTRL_RR __PPCBIT(10)
#define RCTRL_PAL __PPCBITS(11,15)
#define RCTRL_VLEX __PPCBIT(18)
#define RCTRL_FILREN __PPCBIT(19)
@@ -321,7 +330,7 @@
#define RQUEUE_EX6 __PPCBIT(14)
#define RQUEUE_EX7 __PPCBIT(15)
#define RQUEUE_EXn(n) (RQUEUE_EX0 >> (n))
-#define RQUEUE_EX __PPCBITS(0,7)
+#define RQUEUE_EX __PPCBITS(8,15)
#define RQUEUE_EN0 __PPCBIT(24) /* ring is queried for reception */
#define RQUEUE_EN1 __PPCBIT(25)
#define RQUEUE_EN2 __PPCBIT(26)
@@ -332,10 +341,65 @@
#define RQUEUE_EN7 __PPCBIT(31)
#define RQUEUE_EN __PPCBITS(24,31)
#define RQUEUE_ENn(n) (RQUEUE_EN0 >> (n))
+#define RIR0 0x318 /* Ring mapping register 0 */
+#define RIR1 0x31c /* Ring mapping register 1 */
+#define RIR2 0x320 /* Ring mapping register 2 */
+#define RIR3 0x324 /* Ring mapping register 3 */
+#define RIRn(n) (RIR0 + 4*(n))
#define RBIFX 0x330 /* Receive bit field extract control register [TSEC3] */
#define RQFAR 0x334 /* Receive queue filing table address register [TSEC3] */
#define RQFCR 0x338 /* Receive queue filing table control register [TSEC3] */
+#define RQFCR_GPI __PPCBIT(0) /* General purpose interrupt */
+#define RQFCR_HASHTBL __PPCBITS(12,14) /* Select between filer Q value and RIR fileds. */
+#define RQFCR_HASHTBL_Q __SHIFTIN(0,RQFCR_HASHTBL)
+#define RQFCR_HASHTBL_0 __SHIFTIN(1,RQFCR_HASHTBL)
+#define RQFCR_HASHTBL_1 __SHIFTIN(2,RQFCR_HASHTBL)
+#define RQFCR_HASHTBL_2 __SHIFTIN(3,RQFCR_HASHTBL)
+#define RQFCR_HASHTBL_3 __SHIFTIN(4,RQFCR_HASHTBL)
+#define RQFCR_HASH __PPCBIT(15) /* Include parser results in hash */
+#define RQFCR_QUEUE __PPCBITS(16,21) /* Receive queue index */
+#define RQFCR_QUEUE_SET(n) __SHIFTIN((n),RQFCR_QUEUE)
+#define RQFCR_CLE __PPCBIT(22) /* Cluster entry/exit */
+#define RQFCR_REJ __PPCBIT(23) /* Reject frame */
+#define RQFCR_AND __PPCBIT(24) /* AND, in combination with CLE, REJ, and PID match */
+#define RQFCR_CMP __PPCBITS(25,26) /* Comparison operation to perform on the RQPROP entry at this index when PID > 0 */
+#define RQFCR_CMP_EXACT __SHIFTIN(0,RQFCR_CMP)
+#define RQFCR_CMP_MATCH __SHIFTIN(1,RQFCR_CMP)
+#define RQFCR_CMP_NOEXACT __SHIFTIN(2,RQFCR_CMP)
+#define RQFCR_CMP_NOMATCH __SHIFTIN(3,RQFCR_CMP)
+#define RQFCR_PID __PPCBITS(28,31)
+#define RQFCR_PID_MASK 0
+#define RQFCR_PID_PARSE 1
+#define RQFCR_PID_ARB 2
+#define RQFCR_PID_DAH 3
+#define RQFCR_PID_DAL 4
+#define RQFCR_PID_SAH 5
+#define RQFCR_PID_SAL 6
+#define RQFCR_PID_ETY 7
+#define RQFCR_PID_VID 8
+#define RQFCR_PID_PRI 9
+#define RQFCR_PID_TOS 10
+#define RQFCR_PID_L4P 11
+#define RQFCR_PID_DIA 12
+#define RQFCR_PID_SIA 13
+#define RQFCR_PID_DPT 14
+#define RQFCR_PID_SPT 15
#define RQFPR 0x33C /* Receive queue filing table property register [TSEC3] */
+#define RQFPR_PID1_AR __PPCBIT(14) /* ARP response */
+#define RQFPR_PID1_ARQ __PPCBIT(15) /* ARP request */
+#define RQFPR_PID1_EBC __PPCBIT(16) /* destination Ethernet address is to the broadcast address */
+#define RQFPR_PID1_VLN __PPCBIT(17) /* VLAN tag */
+#define RQFPR_PID1_CFI __PPCBIT(18) /* Canonical Format Indicator */
+#define RQFPR_PID1_JUM __PPCBIT(19) /* Jumbo Ethernet frame */
+#define RQFPR_PID1_IPF __PPCBIT(20) /* fragmented IPv4 or IPv6 header */
+#define RQFPR_PID1_IP4 __PPCBIT(22) /* IPv4 header */
+#define RQFPR_PID1_IP6 __PPCBIT(23) /* IPv6 header */
+#define RQFPR_PID1_ICC __PPCBIT(24) /* IPv4 header checksum */
+#define RQFPR_PID1_ICV __PPCBIT(25) /* IPv4 header checksum was verifed correct */
+#define RQFPR_PID1_TCP __PPCBIT(26) /* TCP header */
+#define RQFPR_PID1_UDP __PPCBIT(27) /* UDP header */
+#define RQFPR_PID1_PER __PPCBIT(30) /* parse error */
+#define RQFPR_PID1_EER __PPCBIT(31) /* Ethernet framing error */
#define MRBLR 0x340 /* Maximum receive buffer length register */
#define RBDBPH 0x380 /* Rx data buffer pointer high bits [TSEC3] */
#define RBPTR0 0x384 /* RxBD pointer for ring 0 */
@@ -346,6 +410,7 @@
#define RBPTR5 0x3AC /* RxBD pointer for ring 5 [TSEC3] */
#define RBPTR6 0x3B4 /* RxBD pointer for ring 6 [TSEC3] */
#define RBPTR7 0x3BC /* RxBD pointer for ring 7 [TSEC3] */
+#define RBPTRn(n) (RBPTR0 + 8*(n))
#define RBASEH 0x400 /* RxBD base address high bits [TSEC3] */
#define RBASE0 0x404 /* RxBD base address of ring 0 */
#define RBASE1 0x40C /* RxBD base address of ring 1 [TSEC3] */
@@ -556,6 +621,10 @@
#define RQPRM6 0xC18 /* Receive Queue Parameters register 6 [TSEC3] */
#define RQPRM7 0xC1C /* Receive Queue Parameters register 7 [TSEC3] */
#define RQPRMn(n) (RQPRM0 + 4*(n))
+#define RQPRM_FBTHR __PPCBITS(0,7)
+#define RQPRM_FBTHR_SET(n) __SHIFTIN((n),RQPRM_FBTHR)
+#define RQPRM_LEN __PPCBITS(8,31)
+#define RQPRM_LEN_SET(n) __SHIFTIN((n),RQPRM_LEN)
#define RFBPTR0 0xC44 /* Last Free RxBD pointer for ring 0 [TSEC3] */
#define RFBPTR1 0xC4C /* Last Free RxBD pointer for ring 1 [TSEC3] */
@@ -568,7 +637,7 @@
#define RFBPTRn(n) (RFBPTR0 + 4*(n))
/* 0xc40-0xdff unused */
-/* 0xe00-0xeff 1588 Hardware Assist */
+/* 0xe00-0xeaf 1588 Hardware Assist */
#define TMR_CTRL 0xE00 /* Timer control register [TSEC3] */
#define TMR_TEVENT 0xE04 /* time stamp event register [TSEC3] */
@@ -595,4 +664,32 @@
#define TMR_ETTS2_H 0xEA8 /* Time stamp of general purpose external trigger [TSEC3] */
#define TMR_ETTS2_L 0xEAC /* Time stamp of general purpose external trigger [TSEC3] */
+/* 0xeb0-0xeff Interrupt steering and coalescing */
+
+#define ISRG0 0xeb0 /* Interrupt steering register group 0 */
+#define ISRG1 0xeb4 /* Interrupt steering register group 1 */
+#define ISRGn(n) (ISRG0+4*(n))
+#define ISRG_RRn(n) __PPCBIT(n)
+#define ISRG_TRn(n) __PPCBIT(8+(n))
+
+#define RXIC0 0xed0 /* Ring 0 Rx interrupt coalescing register */
+#define RXIC1 0xed4 /* Ring 1 Rx interrupt coalescing register */
+#define RXIC2 0xed8 /* Ring 2 Rx interrupt coalescing register */
+#define RXIC3 0xedc /* Ring 3 Rx interrupt coalescing register */
+#define RXIC4 0xee0 /* Ring 4 Rx interrupt coalescing register */
+#define RXIC5 0xee4 /* Ring 5 Rx interrupt coalescing register */
+#define RXIC6 0xee8 /* Ring 6 Rx interrupt coalescing register */
+#define RXIC7 0xeec /* Ring 7 Rx interrupt coalescing register */
+#define RXICn(n) (RXIC0+4*(n))
+
+#define TXIC0 0xf10 /* Ring 0 Tx interrupt coalescing register */
+#define TXIC1 0xf14 /* Ring 1 Tx interrupt coalescing register */
+#define TXIC2 0xf18 /* Ring 2 Tx interrupt coalescing register */
+#define TXIC3 0xf1c /* Ring 3 Tx interrupt coalescing register */
+#define TXIC4 0xf20 /* Ring 4 Tx interrupt coalescing register */
+#define TXIC5 0xf24 /* Ring 5 Tx interrupt coalescing register */
+#define TXIC6 0xf28 /* Ring 6 Tx interrupt coalescing register */
+#define TXIC7 0xf2c /* Ring 7 Tx interrupt coalescing register */
+#define TXICn(n) (TXIC0+4*(n))
+
#endif /* _POWERPC_BOOKE_ETSECREG_H_ */
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