[src/trunk]: src/sys/arch/arm/cortex Set caching bits on the TTBR for ARMv7

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/07c16683318d
branches:  trunk
changeset: 787475:07c16683318d
user:      matt <matt%NetBSD.org@localhost>
date:      Thu Jun 20 05:29:01 2013 +0000

description:
Set caching bits on the TTBR for ARMv7
Make sure TTCR is 0

diffstat:

 sys/arch/arm/cortex/a9_mpsubr.S |  9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diffs (25 lines):

diff -r 6d3942dc101c -r 07c16683318d sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S   Thu Jun 20 05:27:31 2013 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S   Thu Jun 20 05:29:01 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: a9_mpsubr.S,v 1.5 2013/06/17 04:38:51 matt Exp $       */
+/*     $NetBSD: a9_mpsubr.S,v 1.6 2013/06/20 05:29:01 matt Exp $       */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -143,8 +143,15 @@
        mcr     p15, 0, r1, c7, c10, 4  /* Drain the write buffers. */
 
        XPUTC(#71)
+       mrc     p15, 0, r2, c0, c0, 5   /* get MPIDR */
+       cmp     r2, #0
+       orrlt   r10, r10, #0x5b         /* MP, cachable (Normal WB) */
+       orrge   r10, r10, #0x1b         /* Non-MP, cacheable, normal WB */
        mcr     p15, 0, r10, c2, c0, 0  /* Set Translation Table Base */
 
+       XPUTC(#49)
+       mcr     p15, 0, r1, c2, c0, 2   /* Set Translation Table Control */
+
        XPUTC(#72)
        mov     r1, #0
        mcr     p15, 0, r1, c8, c7, 0   /* Invalidate TLBs */