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[src/trunk]: src/sys/arch/arm/samsung Add clock controller backend for Exynos...
details: https://anonhg.NetBSD.org/src/rev/687a09bb886a
branches: trunk
changeset: 812227:687a09bb886a
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Dec 05 13:32:27 2015 +0000
description:
Add clock controller backend for Exynos5422. Work in progress.
diffstat:
sys/arch/arm/samsung/exynos5422_clock.c | 623 ++++++++++++++++++++++++++++++++
sys/arch/arm/samsung/exynos5_loc.c | 3 +-
sys/arch/arm/samsung/exynos_clock.h | 83 ++++
sys/arch/arm/samsung/files.exynos | 3 +-
sys/arch/arm/samsung/files.exynos5422 | 8 +
5 files changed, 718 insertions(+), 2 deletions(-)
diffs (truncated from 757 to 300 lines):
diff -r f54500e719ad -r 687a09bb886a sys/arch/arm/samsung/exynos5422_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/samsung/exynos5422_clock.c Sat Dec 05 13:32:27 2015 +0000
@@ -0,0 +1,623 @@
+/* $NetBSD: exynos5422_clock.c,v 1.1 2015/12/05 13:32:27 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: exynos5422_clock.c,v 1.1 2015/12/05 13:32:27 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/atomic.h>
+
+#include <dev/clk/clk_backend.h>
+
+#include <arm/samsung/exynos_reg.h>
+#include <arm/samsung/exynos_var.h>
+#include <arm/samsung/exynos_clock.h>
+
+static struct clk *exynos5422_clock_get(void *, const char *);
+static void exynos5422_clock_put(void *, struct clk *);
+static u_int exynos5422_clock_get_rate(void *, struct clk *);
+static int exynos5422_clock_set_rate(void *, struct clk *, u_int);
+static int exynos5422_clock_enable(void *, struct clk *);
+static int exynos5422_clock_disable(void *, struct clk *);
+static int exynos5422_clock_set_parent(void *, struct clk *, struct clk *);
+static struct clk *exynos5422_clock_get_parent(void *, struct clk *);
+
+static const struct clk_funcs exynos5422_clock_funcs = {
+ .get = exynos5422_clock_get,
+ .put = exynos5422_clock_put,
+ .get_rate = exynos5422_clock_get_rate,
+ .set_rate = exynos5422_clock_set_rate,
+ .enable = exynos5422_clock_enable,
+ .disable = exynos5422_clock_disable,
+ .set_parent = exynos5422_clock_set_parent,
+ .get_parent = exynos5422_clock_get_parent,
+};
+
+#define CLK_FIXED(_name, _rate) { \
+ .base = { .name = (_name) }, .type = EXYNOS_CLK_FIXED, \
+ .u = { .fixed = { .rate = (_rate) } } \
+}
+
+#define CLK_PLL(_name, _parent, _base) { \
+ .base = { .name = (_name) }, .type = EXYNOS_CLK_PLL, \
+ .parent = (_parent), \
+ .u = { \
+ .pll = { \
+ .con0_reg = (_base) + PLL_CON0_OFFSET, \
+ .lock_reg = (_base) + PLL_LOCK_OFFSET, \
+ } \
+ } \
+}
+
+#define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \
+ .base = { .name = (_name), .flags = (_f) }, \
+ .type = EXYNOS_CLK_MUX, \
+ .alias = (_alias), \
+ .u = { \
+ .mux = { \
+ .nparents = __arraycount(_p), \
+ .parents = (_p), \
+ .reg = (_reg), \
+ .bits = (_bits) \
+ } \
+ } \
+}
+
+#define CLK_MUXA(_name, _alias, _reg, _bits, _p) \
+ CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)
+
+#define CLK_MUX(_name, _reg, _bits, _p) \
+ CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)
+
+#define CLK_DIV(_name, _parent, _reg, _bits) { \
+ .base = { .name = (_name) }, .type = EXYNOS_CLK_DIV, \
+ .parent = (_parent), \
+ .u = { \
+ .div = { \
+ .reg = (_reg), \
+ .bits = (_bits) \
+ } \
+ } \
+}
+
+#define CLK_GATE(_name, _parent, _reg, _bits, _f) { \
+ .base = { .name = (_name), .flags = (_f) }, \
+ .type = EXYNOS_CLK_GATE, \
+ .parent = (_parent), \
+ .u = { \
+ .gate = { \
+ .reg = (_reg), \
+ .bits = (_bits) \
+ } \
+ } \
+}
+
+#define EXYNOS5422_APLL_BASE 0x00000
+#define EXYNOS5422_CPLL_BASE 0x10020
+#define EXYNOS5422_DPLL_BASE 0x10030
+#define EXYNOS5422_EPLL_BASE 0x10040
+#define EXYNOS5422_RPLL_BASE 0x10050
+#define EXYNOS5422_IPLL_BASE 0x10060
+#define EXYNOS5422_SPLL_BASE 0x10070
+#define EXYNOS5422_VPLL_BASE 0x10080
+#define EXYNOS5422_MPLL_BASE 0x10090
+#define EXYNOS5422_BPLL_BASE 0x20010
+#define EXYNOS5422_KPLL_BASE 0x28000
+
+#define EXYNOS5422_SRC_CPU 0x00200
+#define EXYNOS5422_SRC_TOP0 0x10200
+#define EXYNOS5422_SRC_TOP1 0x10204
+#define EXYNOS5422_SRC_TOP2 0x10208
+#define EXYNOS5422_SRC_TOP3 0x1020c
+#define EXYNOS5422_SRC_TOP4 0x10210
+#define EXYNOS5422_SRC_TOP5 0x10214
+#define EXYNOS5422_SRC_TOP6 0x10218
+#define EXYNOS5422_SRC_TOP7 0x1021c
+#define EXYNOS5422_SRC_DISP10 0x1022c
+#define EXYNOS5422_SRC_MAU 0x10240
+#define EXYNOS5422_SRC_FSYS 0x10244
+#define EXYNOS5422_SRC_PERIC0 0x10250
+#define EXYNOS5422_SRC_PERIC1 0x10254
+#define EXYNOS5422_SRC_ISP 0x10270
+#define EXYNOS5422_SRC_TOP10 0x10280
+#define EXYNOS5422_SRC_TOP11 0x10280
+#define EXYNOS5422_SRC_TOP12 0x10280
+
+#define EXYNOS5422_DIV_FSYS1 0x1054c
+
+#define EXYNOS5422_GATE_TOP_SCLK_FSYS 0x10840
+
+static const char *mout_cpll_p[] = { "fin_pll", "fout_cpll" };
+static const char *mout_dpll_p[] = { "fin_pll", "fout_dpll" };
+static const char *mout_mpll_p[] = { "fin_pll", "fout_mpll" };
+static const char *mout_spll_p[] = { "fin_pll", "fout_spll" };
+static const char *mout_ipll_p[] = { "fin_pll", "fout_ipll" };
+static const char *mout_epll_p[] = { "fin_pll", "fout_epll" };
+static const char *mout_rpll_p[] = { "fin_pll", "fout_rpll" };
+static const char *mout_group2_p[] =
+ { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
+ "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+
+static struct exynos_clk exynos5422_clocks[] = {
+ CLK_FIXED("fin_pll", EXYNOS_F_IN_FREQ),
+
+ CLK_PLL("fout_apll", "fin_pll", EXYNOS5422_APLL_BASE),
+ CLK_PLL("fout_cpll", "fin_pll", EXYNOS5422_CPLL_BASE),
+ CLK_PLL("fout_dpll", "fin_pll", EXYNOS5422_DPLL_BASE),
+ CLK_PLL("fout_epll", "fin_pll", EXYNOS5422_EPLL_BASE),
+ CLK_PLL("fout_rpll", "fin_pll", EXYNOS5422_RPLL_BASE),
+ CLK_PLL("fout_ipll", "fin_pll", EXYNOS5422_IPLL_BASE),
+ CLK_PLL("fout_spll", "fin_pll", EXYNOS5422_SPLL_BASE),
+ CLK_PLL("fout_vpll", "fin_pll", EXYNOS5422_VPLL_BASE),
+ CLK_PLL("fout_mpll", "fin_pll", EXYNOS5422_MPLL_BASE),
+ CLK_PLL("fout_bpll", "fin_pll", EXYNOS5422_BPLL_BASE),
+ CLK_PLL("fout_kpll", "fin_pll", EXYNOS5422_KPLL_BASE),
+
+ CLK_MUXA("sclk_cpll", "mout_cpll", EXYNOS5422_SRC_TOP6, __BIT(28),
+ mout_cpll_p),
+ CLK_MUXA("sclk_dpll", "mout_dpll", EXYNOS5422_SRC_TOP6, __BIT(24),
+ mout_dpll_p),
+ CLK_MUXA("sclk_mpll", "mout_mpll", EXYNOS5422_SRC_TOP6, __BIT(0),
+ mout_mpll_p),
+ CLK_MUXA("sclk_spll", "mout_spll", EXYNOS5422_SRC_TOP6, __BIT(8),
+ mout_spll_p),
+ CLK_MUXA("sclk_ipll", "mout_ipll", EXYNOS5422_SRC_TOP6, __BIT(12),
+ mout_ipll_p),
+ CLK_MUXF("sclk_epll", "mout_epll", EXYNOS5422_SRC_TOP6, __BIT(20),
+ CLK_SET_RATE_PARENT, mout_epll_p),
+ CLK_MUXF("sclk_rpll", "mout_rpll", EXYNOS5422_SRC_TOP6, __BIT(16),
+ CLK_SET_RATE_PARENT, mout_rpll_p),
+
+ CLK_MUX("mout_mmc0", EXYNOS5422_SRC_FSYS, __BITS(10,8),
+ mout_group2_p),
+ CLK_MUX("mout_mmc1", EXYNOS5422_SRC_FSYS, __BITS(14,12),
+ mout_group2_p),
+ CLK_MUX("mout_mmc2", EXYNOS5422_SRC_FSYS, __BITS(18,16),
+ mout_group2_p),
+
+ CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)),
+ CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10)),
+ CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5422_DIV_FSYS1, __BITS(29,20)),
+
+ CLK_GATE("sclk_mmc0", "dout_mmc0", EXYNOS5422_GATE_TOP_SCLK_FSYS,
+ __BIT(0), CLK_SET_RATE_PARENT),
+ CLK_GATE("sclk_mmc1", "dout_mmc1", EXYNOS5422_GATE_TOP_SCLK_FSYS,
+ __BIT(1), CLK_SET_RATE_PARENT),
+ CLK_GATE("sclk_mmc2", "dout_mmc2", EXYNOS5422_GATE_TOP_SCLK_FSYS,
+ __BIT(2), CLK_SET_RATE_PARENT),
+};
+
+static int exynos5422_clock_match(device_t, cfdata_t, void *);
+static void exynos5422_clock_attach(device_t, device_t, void *);
+
+struct exynos5422_clock_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
+
+static void exynos5422_clock_print_header(void);
+static void exynos5422_clock_print(struct exynos5422_clock_softc *,
+ struct exynos_clk *);
+
+CFATTACH_DECL_NEW(exynos5422_clock, sizeof(struct exynos5422_clock_softc),
+ exynos5422_clock_match, exynos5422_clock_attach, NULL, NULL);
+
+#define CLOCK_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define CLOCK_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static int
+exynos5422_clock_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return IS_EXYNOS5422_P();
+}
+
+static void
+exynos5422_clock_attach(device_t parent, device_t self, void *aux)
+{
+ struct exynos5422_clock_softc * const sc = device_private(self);
+ struct exyo_attach_args * const exyo = aux;
+ const struct exyo_locators *loc = &exyo->exyo_loc;
+
+ sc->sc_dev = self;
+ sc->sc_bst = exyo->exyo_core_bst;
+ bus_space_subregion(exyo->exyo_core_bst, exyo->exyo_core_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
+ aprint_naive("\n");
+ aprint_normal(": Exynos5422 Clock Controller\n");
+
+ clk_backend_register("exynos5422", &exynos5422_clock_funcs, sc);
+
+ exynos5422_clock_print_header();
+ for (u_int n = 0; n < __arraycount(exynos5422_clocks); n++) {
+ exynos5422_clock_print(sc, &exynos5422_clocks[n]);
+ }
+}
+
+static struct exynos_clk *
+exynos5422_clock_find(const char *name)
+{
+ u_int n;
+
+ for (n = 0; n < __arraycount(exynos5422_clocks); n++) {
+ if (strcmp(exynos5422_clocks[n].base.name, name) == 0) {
+ return &exynos5422_clocks[n];
+ }
+ }
+
+ return NULL;
+}
+
+static void
+exynos5422_clock_print_header(void)
+{
+ printf(" %-10s %2s %-10s %-5s %10s\n",
+ "clock", "", "parent", "type", "rate");
+ printf(" %-10s %2s %-10s %-5s %10s\n",
+ "=====", "", "======", "====", "====");
+}
+
+static void
+exynos5422_clock_print(struct exynos5422_clock_softc *sc,
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