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[src/trunk]: src/sys/arch/arm/arm32 Collapse multiple inlines and move repeat...
details: https://anonhg.NetBSD.org/src/rev/e3b6cc632795
branches: trunk
changeset: 787788:e3b6cc632795
user: matt <matt%NetBSD.org@localhost>
date: Wed Jul 03 15:24:35 2013 +0000
description:
Collapse multiple inlines and move repeated tests into them.
No functional change.
diffstat:
sys/arch/arm/arm32/pmap.c | 269 ++++++++++++++-------------------------------
1 files changed, 86 insertions(+), 183 deletions(-)
diffs (truncated from 513 to 300 lines):
diff -r df5ae09a677a -r e3b6cc632795 sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Wed Jul 03 15:21:35 2013 +0000
+++ b/sys/arch/arm/arm32/pmap.c Wed Jul 03 15:24:35 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.258 2013/07/03 05:23:04 matt Exp $ */
+/* $NetBSD: pmap.c,v 1.259 2013/07/03 15:24:35 matt Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -212,7 +212,7 @@
#include <arm/cpuconf.h>
#include <arm/arm32/katelib.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.258 2013/07/03 05:23:04 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.259 2013/07/03 15:24:35 matt Exp $");
#ifdef PMAP_DEBUG
@@ -723,25 +723,20 @@
* given time.
*/
static inline void
-pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va)
+pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags)
{
-
- if (pm->pm_cstate.cs_tlb_id)
- cpu_tlb_flushID_SE(va);
-}
-
-static inline void
-pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va)
-{
-
- if (pm->pm_cstate.cs_tlb_d)
- cpu_tlb_flushD_SE(va);
+ if (pm->pm_cstate.cs_tlb_id != 0) {
+ if (PV_BEEN_EXECD(flags)) {
+ cpu_tlb_flushID_SE(va);
+ } else if (PV_BEEN_REFD(flags)) {
+ cpu_tlb_flushD_SE(va);
+ }
+ }
}
static inline void
pmap_tlb_flushID(pmap_t pm)
{
-
if (pm->pm_cstate.cs_tlb_id) {
cpu_tlb_flushID();
#if ARM_MMU_V7 == 0
@@ -753,14 +748,13 @@
* This is not true for other CPUs.
*/
pm->pm_cstate.cs_tlb = 0;
-#endif
+#endif /* ARM_MMU_V7 */
}
}
static inline void
pmap_tlb_flushD(pmap_t pm)
{
-
if (pm->pm_cstate.cs_tlb_d) {
cpu_tlb_flushD();
#if ARM_MMU_V7 == 0
@@ -772,49 +766,37 @@
* This is not true for other CPUs.
*/
pm->pm_cstate.cs_tlb_d = 0;
-#endif
}
+#endif /* ARM_MMU_V7 */
}
#ifdef PMAP_CACHE_VIVT
static inline void
-pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len)
+pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags)
{
- if (pm->pm_cstate.cs_cache_id) {
- cpu_idcache_wbinv_range(va, len);
+ if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) {
+ cpu_idcache_wbinv_range(va, PAGE_SIZE);
+ } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) {
+ if (do_inv) {
+ if (flags & PVF_WRITE)
+ cpu_dcache_wbinv_range(va, PAGE_SIZE);
+ else
+ cpu_dcache_inv_range(va, PAGE_SIZE);
+ } else if (flags & PVF_WRITE) {
+ cpu_dcache_wb_range(va, PAGE_SIZE);
+ }
}
}
static inline void
-pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len,
- bool do_inv, bool rd_only)
+pmap_cache_wbinv_all(pmap_t pm, u_int flags)
{
-
- if (pm->pm_cstate.cs_cache_d) {
- if (do_inv) {
- if (rd_only)
- cpu_dcache_inv_range(va, len);
- else
- cpu_dcache_wbinv_range(va, len);
- } else
- if (!rd_only)
- cpu_dcache_wb_range(va, len);
- }
-}
-
-static inline void
-pmap_idcache_wbinv_all(pmap_t pm)
-{
- if (pm->pm_cstate.cs_cache_id) {
- cpu_idcache_wbinv_all();
- pm->pm_cstate.cs_cache = 0;
- }
-}
-
-static inline void
-pmap_dcache_wbinv_all(pmap_t pm)
-{
- if (pm->pm_cstate.cs_cache_d) {
+ if (PV_BEEN_EXECD(flags)) {
+ if (pm->pm_cstate.cs_cache_id) {
+ cpu_idcache_wbinv_all();
+ pm->pm_cstate.cs_cache = 0;
+ }
+ } else if (pm->pm_cstate.cs_cache_d) {
cpu_dcache_wbinv_all();
pm->pm_cstate.cs_cache_d = 0;
}
@@ -1806,25 +1788,14 @@
ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
pte = *ptep & ~L2_S_CACHE_MASK;
- if ((va != pv->pv_va || pm != pv->pv_pmap) &&
- l2pte_valid(pte)) {
- if (PV_BEEN_EXECD(pv->pv_flags)) {
+ if ((va != pv->pv_va || pm != pv->pv_pmap)
+ && l2pte_valid(pte)) {
#ifdef PMAP_CACHE_VIVT
- pmap_idcache_wbinv_range(pv->pv_pmap,
- pv->pv_va, PAGE_SIZE);
-#endif
- pmap_tlb_flushID_SE(pv->pv_pmap,
- pv->pv_va);
- } else
- if (PV_BEEN_REFD(pv->pv_flags)) {
-#ifdef PMAP_CACHE_VIVT
- pmap_dcache_wb_range(pv->pv_pmap,
- pv->pv_va, PAGE_SIZE, true,
- (pv->pv_flags & PVF_WRITE) == 0);
-#endif
- pmap_tlb_flushD_SE(pv->pv_pmap,
- pv->pv_va);
- }
+ pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va,
+ true, pv->pv_flags);
+#endif
+ pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va,
+ pv->pv_flags);
}
*ptep = pte;
@@ -1850,14 +1821,8 @@
pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
if (l2pte_valid(pte)) {
- if (PV_BEEN_EXECD(pv->pv_flags)) {
- pmap_tlb_flushID_SE(pv->pv_pmap,
- pv->pv_va);
- } else
- if (PV_BEEN_REFD(pv->pv_flags)) {
- pmap_tlb_flushD_SE(pv->pv_pmap,
- pv->pv_va);
- }
+ pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va,
+ pv->pv_flags);
}
*ptep = pte;
@@ -2149,11 +2114,8 @@
continue;
if (l2pte_valid(pte)) {
- if (PV_BEEN_EXECD(pv->pv_flags)) {
- pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
- } else if (PV_BEEN_REFD(pv->pv_flags)) {
- pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
- }
+ pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va,
+ pv->pv_flags);
}
*ptep = pte;
@@ -2269,14 +2231,9 @@
* is current if it is flush it, otherwise it
* won't be in the cache
*/
- if (PV_BEEN_EXECD(oflags))
- pmap_idcache_wbinv_range(pm, pv->pv_va,
- PAGE_SIZE);
- else
- if (PV_BEEN_REFD(oflags))
- pmap_dcache_wb_range(pm, pv->pv_va,
- PAGE_SIZE,
- (maskbits & PVF_REF) != 0, false);
+ pmap_cache_wbinv_page(pm, pv->pv_va,
+ (maskbits & PVF_REF) != 0,
+ oflags|PVF_WRITE);
}
#endif
@@ -2310,9 +2267,9 @@
}
if (maskbits & PVF_REF) {
- if ((pv->pv_flags & PVF_NC) == 0 &&
- (maskbits & (PVF_WRITE|PVF_MOD)) == 0 &&
- l2pte_valid(npte)) {
+ if ((pv->pv_flags & PVF_NC) == 0
+ && (maskbits & (PVF_WRITE|PVF_MOD)) == 0
+ && l2pte_valid(npte)) {
#ifdef PMAP_CACHE_VIVT
/*
* Check npte here; we may have already
@@ -2320,15 +2277,8 @@
* of the PTE is the same for opte and
* npte.
*/
- /* XXXJRT need idcache_inv_range */
- if (PV_BEEN_EXECD(oflags))
- pmap_idcache_wbinv_range(pm,
- pv->pv_va, PAGE_SIZE);
- else
- if (PV_BEEN_REFD(oflags))
- pmap_dcache_wb_range(pm,
- pv->pv_va, PAGE_SIZE,
- true, true);
+ pmap_cache_wbinv_page(pm, pv->pv_va, true,
+ oflags);
#endif
}
@@ -2345,11 +2295,7 @@
*ptep = npte;
PTE_SYNC(ptep);
/* Flush the TLB entry if a current pmap. */
- if (PV_BEEN_EXECD(oflags))
- pmap_tlb_flushID_SE(pm, pv->pv_va);
- else
- if (PV_BEEN_REFD(oflags))
- pmap_tlb_flushD_SE(pm, pv->pv_va);
+ pmap_tlb_flush_SE(pm, pv->pv_va, oflags);
}
pmap_release_pmap_lock(pm);
@@ -2448,19 +2394,12 @@
}
if (page_to_clean) {
- if (PV_BEEN_EXECD(flags))
- pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
- PAGE_SIZE);
- else
- pmap_dcache_wb_range(pm_to_clean, page_to_clean,
- PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
+ pmap_cache_wbinv_page(pm_to_clean, page_to_clean,
+ !is_src, flags | PVF_REF);
} else if (cache_needs_cleaning) {
pmap_t const pm = curproc->p_vmspace->vm_map.pmap;
- if (PV_BEEN_EXECD(flags))
- pmap_idcache_wbinv_all(pm);
- else
- pmap_dcache_wbinv_all(pm);
+ pmap_cache_wbinv_all(pm, flags);
return (1);
}
return (0);
@@ -2487,7 +2426,7 @@
return;
KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED);
- pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset);
+ pmap_tlb_flush_SE(pmap_kernel(), cdstp + va_offset, PVF_REF | PVF_EXEC);
/*
* Set up a PTE with the right coloring to flush existing cache lines.
*/
@@ -2506,7 +2445,7 @@
*/
*ptep = 0;
PTE_SYNC(ptep);
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