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[src/trunk]: src/sys/arch/arm/nvidia Add SOC_THERM temperature sensor driver:
details: https://anonhg.NetBSD.org/src/rev/898cb21ee227
branches: trunk
changeset: 811912:898cb21ee227
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Nov 21 22:55:32 2015 +0000
description:
Add SOC_THERM temperature sensor driver:
# envstat -d tegrasoctherm0
Current CritMax WarnMax WarnMin CritMin Unit
CPU0: 27.500 degC
CPU1: 27.500 degC
CPU2: 29.500 degC
CPU3: 29.000 degC
MEM0: 26.500 degC
MEM1: 27.000 degC
GPU: 27.000 degC
PLLX: 28.000 degC
diffstat:
sys/arch/arm/nvidia/files.tegra | 7 +-
sys/arch/arm/nvidia/tegra_car.c | 37 +++-
sys/arch/arm/nvidia/tegra_carreg.h | 13 +-
sys/arch/arm/nvidia/tegra_intr.h | 3 +-
sys/arch/arm/nvidia/tegra_io.c | 6 +-
sys/arch/arm/nvidia/tegra_reg.h | 4 +-
sys/arch/arm/nvidia/tegra_soctherm.c | 329 ++++++++++++++++++++++++++++++++
sys/arch/arm/nvidia/tegra_socthermreg.h | 68 ++++++
sys/arch/arm/nvidia/tegra_var.h | 3 +-
9 files changed, 461 insertions(+), 9 deletions(-)
diffs (truncated from 601 to 300 lines):
diff -r 87c4153a0c7f -r 898cb21ee227 sys/arch/arm/nvidia/files.tegra
--- a/sys/arch/arm/nvidia/files.tegra Sat Nov 21 22:52:31 2015 +0000
+++ b/sys/arch/arm/nvidia/files.tegra Sat Nov 21 22:55:32 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.23 2015/11/21 12:09:39 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.24 2015/11/21 22:55:32 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -91,6 +91,11 @@
attach sdhc at tegraio with tegra_sdhc
file arch/arm/nvidia/tegra_sdhc.c tegra_sdhc
+# Thermal throttling controller
+device tegrasoctherm: sysmon_envsys
+attach tegrasoctherm at tegraio with tegra_soctherm
+file arch/arm/nvidia/tegra_soctherm.c tegra_soctherm
+
# PCIE
device tegrapcie: pcibus
attach tegrapcie at tegraio with tegra_pcie
diff -r 87c4153a0c7f -r 898cb21ee227 sys/arch/arm/nvidia/tegra_car.c
--- a/sys/arch/arm/nvidia/tegra_car.c Sat Nov 21 22:52:31 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_car.c Sat Nov 21 22:55:32 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_car.c,v 1.29 2015/11/21 12:09:39 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.30 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.29 2015/11/21 12:09:39 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.30 2015/11/21 22:55:32 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -882,3 +882,36 @@
tegra_reg_set_clear(bst, bsh, CAR_CLK_ENB_H_SET_REG, 0, CAR_DEV_H_FUSE);
}
+
+void
+tegra_car_soctherm_enable(void)
+{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+
+ tegra_car_get_bs(&bst, &bsh);
+
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_SET_REG, CAR_DEV_U_SOC_THERM);
+
+ const u_int soctherm_rate = 51000000;
+ const u_int soctherm_div =
+ howmany(tegra_car_pllp0_rate() * 2, soctherm_rate) - 2;
+ bus_space_write_4(bst, bsh, CAR_CLKSRC_SOC_THERM_REG,
+ __SHIFTIN(soctherm_div, CAR_CLKSRC_SOC_THERM_DIV) |
+ __SHIFTIN(CAR_CLKSRC_SOC_THERM_SRC_PLLP_OUT0,
+ CAR_CLKSRC_SOC_THERM_SRC));
+ delay(20);
+
+ const u_int tsensor_rate = 400000;
+ const u_int tsensor_div =
+ howmany(TEGRA_REF_FREQ * 2, tsensor_rate) - 2;
+ bus_space_write_4(bst, bsh, CAR_CLKSRC_TSENSOR_REG,
+ __SHIFTIN(tsensor_div, CAR_CLKSRC_TSENSOR_DIV) |
+ __SHIFTIN(CAR_CLKSRC_TSENSOR_SRC_CLK_M, CAR_CLKSRC_TSENSOR_SRC));
+ delay(20);
+
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_TSENSOR);
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_SOC_THERM);
+
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_SOC_THERM);
+}
diff -r 87c4153a0c7f -r 898cb21ee227 sys/arch/arm/nvidia/tegra_carreg.h
--- a/sys/arch/arm/nvidia/tegra_carreg.h Sat Nov 21 22:52:31 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_carreg.h Sat Nov 21 22:55:32 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_carreg.h,v 1.21 2015/10/17 21:16:09 jmcneill Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.22 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -358,6 +358,7 @@
#define CAR_DEV_V_I2C4 __BIT(7)
#define CAR_DEV_V_I2S4 __BIT(6)
#define CAR_DEV_V_I2S3 __BIT(5)
+#define CAR_DEV_V_TSENSOR __BIT(4)
#define CAR_DEV_V_MSELECT __BIT(3)
#define CAR_DEV_V_CPULP __BIT(1)
#define CAR_DEV_V_CPUG __BIT(0)
@@ -395,6 +396,11 @@
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM 0
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ 8
+#define CAR_CLKSRC_TSENSOR_REG 0x3b8
+#define CAR_CLKSRC_TSENSOR_SRC __BITS(31,29)
+#define CAR_CLKSRC_TSENSOR_SRC_CLK_M 4
+#define CAR_CLKSRC_TSENSOR_DIV __BITS(7,0)
+
#define CAR_CLKSRC_HDA2CODEC_2X_REG 0x3e4
#define CAR_CLKSRC_HDA2CODEC_2X_SRC __BITS(31,29)
#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0 0
@@ -477,6 +483,11 @@
#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY __BITS(15,8)
#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)
+#define CAR_CLKSRC_SOC_THERM_REG 0x644
+#define CAR_CLKSRC_SOC_THERM_SRC __BITS(31,29)
+#define CAR_CLKSRC_SOC_THERM_SRC_PLLP_OUT0 2
+#define CAR_CLKSRC_SOC_THERM_DIV __BITS(7,0)
+
#define CAR_CLKSRC_HDMI_AUDIO_REG 0x668
#define CAR_CLKSRC_HDMI_AUDIO_SRC __BITS(31,29)
#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLP_OUT0 0
diff -r 87c4153a0c7f -r 898cb21ee227 sys/arch/arm/nvidia/tegra_intr.h
--- a/sys/arch/arm/nvidia/tegra_intr.h Sat Nov 21 22:52:31 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_intr.h Sat Nov 21 22:55:32 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_intr.h,v 1.10 2015/11/18 17:01:39 jakllsch Exp $ */
+/* $NetBSD: tegra_intr.h,v 1.11 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -53,6 +53,7 @@
#define TEGRA_INTR_TMR3 TEGRA_INTR(41)
#define TEGRA_INTR_TMR4 TEGRA_INTR(42)
#define TEGRA_INTR_UARTC TEGRA_INTR(46)
+#define TEGRA_INTR_THERMAL TEGRA_INTR(48)
#define TEGRA_INTR_I2C5 TEGRA_INTR(53)
#define TEGRA_INTR_I2C6 TEGRA_INTR(63)
#define TEGRA_INTR_HOST1X_SYNCPT_COP TEGRA_INTR(64)
diff -r 87c4153a0c7f -r 898cb21ee227 sys/arch/arm/nvidia/tegra_io.c
--- a/sys/arch/arm/nvidia/tegra_io.c Sat Nov 21 22:52:31 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_io.c Sat Nov 21 22:55:32 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_io.c,v 1.20 2015/11/21 12:09:39 jmcneill Exp $ */
+/* $NetBSD: tegra_io.c,v 1.21 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.20 2015/11/21 12:09:39 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.21 2015/11/21 22:55:32 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -117,6 +117,8 @@
TEGRA_HDA_OFFSET, TEGRA_HDA_SIZE, NOPORT, TEGRA_INTR_HDA },
{ "tegracec",
TEGRA_CEC_OFFSET, TEGRA_CEC_SIZE, NOPORT, TEGRA_INTR_CEC },
+ { "tegrasoctherm",
+ TEGRA_SOC_THERM_OFFSET, TEGRA_SOC_THERM_SIZE, NOPORT, TEGRA_INTR_THERMAL },
};
static const struct tegra_locators tegra_ahb_a2_locators[] = {
diff -r 87c4153a0c7f -r 898cb21ee227 sys/arch/arm/nvidia/tegra_reg.h
--- a/sys/arch/arm/nvidia/tegra_reg.h Sat Nov 21 22:52:31 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_reg.h Sat Nov 21 22:55:32 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_reg.h,v 1.19 2015/11/21 12:09:39 jmcneill Exp $ */
+/* $NetBSD: tegra_reg.h,v 1.20 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -130,6 +130,8 @@
#define TEGRA_SDMMC4_SIZE 0x200
#define TEGRA_XUSB_DEV_OFFSET 0x000d0000
#define TEGRA_XUSB_DEV_SIZE 0xa000
+#define TEGRA_SOC_THERM_OFFSET 0x000e2000
+#define TEGRA_SOC_THERM_SIZE 0x1000
/* PPSB */
#define TEGRA_TIMER_OFFSET 0x00005000
diff -r 87c4153a0c7f -r 898cb21ee227 sys/arch/arm/nvidia/tegra_soctherm.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/nvidia/tegra_soctherm.c Sat Nov 21 22:55:32 2015 +0000
@@ -0,0 +1,329 @@
+/* $NetBSD: tegra_soctherm.c,v 1.1 2015/11/21 22:55:32 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.1 2015/11/21 22:55:32 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/kmem.h>
+
+#include <dev/sysmon/sysmonvar.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_socthermreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#define FUSE_TSENSOR_CALIB_CP_TS_BASE __BITS(12,0)
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE __BITS(25,13)
+
+#define FUSE_TSENSOR8_CALIB_REG 0x180
+#define FUSE_TSENSOR8_CALIB_CP_TS_BASE __BITS(9,0)
+#define FUSE_TSENSOR8_CALIB_FT_TS_BASE __BITS(20,10)
+
+#define FUSE_SPARE_REALIGNMENT_REG 0x1fc
+#define FUSE_SPARE_REALIGNMENT_CP __BITS(5,0)
+#define FUSE_SPARE_REALIGNMENT_FT __BITS(25,21)
+
+static int tegra_soctherm_match(device_t, cfdata_t, void *);
+static void tegra_soctherm_attach(device_t, device_t, void *);
+
+struct tegra_soctherm_config {
+ uint32_t init_pdiv;
+ uint32_t init_hotspot_off;
+ uint32_t nominal_calib_ft;
+ uint32_t nominal_calib_cp;
+ uint32_t tall;
+ uint32_t tsample;
+ uint32_t tiddq_en;
+ uint32_t ten_count;
+ uint32_t pdiv;
+ uint32_t tsample_ate;
+ uint32_t pdiv_ate;
+};
+
+static const struct tegra_soctherm_config tegra124_soctherm_config = {
+ .init_pdiv = 0x8888,
+ .init_hotspot_off = 0x60600,
+ .nominal_calib_ft = 105,
+ .nominal_calib_cp = 25,
+ .tall = 16300,
+ .tsample = 120,
+ .tiddq_en = 1,
+ .ten_count = 1,
+ .pdiv = 8,
+ .tsample_ate = 480,
+ .pdiv_ate = 8
+};
+
+struct tegra_soctherm_sensor {
+ envsys_data_t s_data;
+ u_int s_base;
+ u_int s_fuse;
+ int s_fuse_corr_alpha;
+ int s_fuse_corr_beta;
+ int16_t s_therm_a;
+ int16_t s_therm_b;
+};
+
+static const struct tegra_soctherm_sensor tegra_soctherm_sensors[] = {
+ { .s_data = { .desc = "CPU0" }, .s_base = 0x0c0, .s_fuse = 0x098,
+ .s_fuse_corr_alpha = 1135400, .s_fuse_corr_beta = -6266900 },
+ { .s_data = { .desc = "CPU1" }, .s_base = 0x0e0, .s_fuse = 0x084,
+ .s_fuse_corr_alpha = 1122220, .s_fuse_corr_beta = -5700700 },
+ { .s_data = { .desc = "CPU2" }, .s_base = 0x100, .s_fuse = 0x088,
+ .s_fuse_corr_alpha = 1127000, .s_fuse_corr_beta = -6768200 },
+ { .s_data = { .desc = "CPU3" }, .s_base = 0x120, .s_fuse = 0x12c,
+ .s_fuse_corr_alpha = 1110900, .s_fuse_corr_beta = -6232000 },
+ { .s_data = { .desc = "MEM0" }, .s_base = 0x140, .s_fuse = 0x158,
+ .s_fuse_corr_alpha = 1122300, .s_fuse_corr_beta = -5936400 },
+ { .s_data = { .desc = "MEM1" }, .s_base = 0x160, .s_fuse = 0x15c,
+ .s_fuse_corr_alpha = 1145700, .s_fuse_corr_beta = -7124600 },
+ { .s_data = { .desc = "GPU" }, .s_base = 0x180, .s_fuse = 0x154,
+ .s_fuse_corr_alpha = 1120100, .s_fuse_corr_beta = -6000500 },
+ { .s_data = { .desc = "PLLX" }, .s_base = 0x1a0, .s_fuse = 0x160,
+ .s_fuse_corr_alpha = 1106500, .s_fuse_corr_beta = -6729300 },
+};
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