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[src/trunk]: src/sys/arch A80 I2C support
details: https://anonhg.NetBSD.org/src/rev/04d52637bb29
branches: trunk
changeset: 804899:04d52637bb29
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Dec 05 15:25:27 2014 +0000
description:
A80 I2C support
diffstat:
sys/arch/arm/allwinner/awin_io.c | 7 +++++-
sys/arch/arm/allwinner/awin_reg.h | 22 +++++++++++++++++++
sys/arch/arm/allwinner/awin_twi.c | 42 ++++++++++++++++++++++++++++++-------
sys/arch/evbarm/conf/ALLWINNER_A80 | 14 +++++++-----
4 files changed, 70 insertions(+), 15 deletions(-)
diffs (192 lines):
diff -r c8d6217e5dd3 -r 04d52637bb29 sys/arch/arm/allwinner/awin_io.c
--- a/sys/arch/arm/allwinner/awin_io.c Fri Dec 05 14:46:04 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_io.c Fri Dec 05 15:25:27 2014 +0000
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.32 2014/12/05 14:36:44 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.33 2014/12/05 15:25:27 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -151,6 +151,11 @@
{ "awiniic", OFFANDSIZE(TWI1), 1, AWIN_A31_IRQ_TWI1, A31 },
{ "awiniic", OFFANDSIZE(TWI2), 2, AWIN_A31_IRQ_TWI2, A31 },
{ "awiniic", OFFANDSIZE(TWI3), 3, AWIN_A31_IRQ_TWI3, A31 },
+ { "awiniic", OFFANDSIZE(A80_TWI0), 0, AWIN_A80_IRQ_TWI0, A80 },
+ { "awiniic", OFFANDSIZE(A80_TWI1), 1, AWIN_A80_IRQ_TWI1, A80 },
+ { "awiniic", OFFANDSIZE(A80_TWI2), 2, AWIN_A80_IRQ_TWI2, A80 },
+ { "awiniic", OFFANDSIZE(A80_TWI3), 3, AWIN_A80_IRQ_TWI3, A80 },
+ { "awiniic", OFFANDSIZE(A80_TWI4), 4, AWIN_A80_IRQ_TWI4, A80 },
{ "awinp2wi", OFFANDSIZE(A31_P2WI), NOPORT, AWIN_A31_IRQ_P2WI, A31 },
{ "spi", OFFANDSIZE(SPI0), 0, AWIN_IRQ_SPI0, AANY },
{ "spi", OFFANDSIZE(SPI1), 1, AWIN_IRQ_SPI1, AANY },
diff -r c8d6217e5dd3 -r 04d52637bb29 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Fri Dec 05 14:46:04 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Fri Dec 05 15:25:27 2014 +0000
@@ -2725,8 +2725,20 @@
#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING0_SD __BIT(8)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI4 __BIT(4)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI2 __BIT(3)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI3 __BIT(2)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI1 __BIT(1)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI0 __BIT(0)
+
#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST0_SD __BIT(8)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI4 __BIT(4)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI3 __BIT(3)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI2 __BIT(2)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI1 __BIT(1)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI0 __BIT(0)
+
#define AWIN_A80_CCU_SCLK_SDMMC_SCLK_GATING __BIT(31)
#define AWIN_A80_CCU_SCLK_SDMMC_CLK_SRC_SEL __BITS(27,24)
#define AWIN_A80_CCU_SCLK_SDMMC_CLK_SRC_SEL_OSC24M 0
@@ -2739,6 +2751,8 @@
#define AWIN_A80_PIO_PA_PINS 18
#define AWIN_A80_PIO_PB_PINS 20
+#define AWIN_A80_PIO_PB_TWI4_FUNC 4
+#define AWIN_A80_PIO_PB_TWI4_PINS 0x00018000 /* PB pins 16-15 */
#define AWIN_A80_PIO_PC_PINS 20
#define AWIN_A80_PIO_PC_SDMMC2_FUNC 3
@@ -2755,7 +2769,15 @@
#define AWIN_A80_PIO_PG_PINS 16
#define AWIN_A80_PIO_PG_SDMMC1_FUNC 2
#define AWIN_A80_PIO_PG_SDMMC1_PINS 0x0000003f /* PG pins 5-0 */
+#define AWIN_A80_PIO_PG_TWI3_FUNC 2
+#define AWIN_A80_PIO_PG_TWI3_PINS 0x00000c00 /* PG pins 11-10 */
#define AWIN_A80_PIO_PH_PINS 22
+#define AWIN_A80_PIO_PH_TWI0_FUNC 2
+#define AWIN_A80_PIO_PH_TWI0_PINS 0x00000003 /* PH pins 1-0 */
+#define AWIN_A80_PIO_PH_TWI1_FUNC 2
+#define AWIN_A80_PIO_PH_TWI1_PINS 0x0000000c /* PH pins 3-2 */
+#define AWIN_A80_PIO_PH_TWI2_FUNC 2
+#define AWIN_A80_PIO_PH_TWI2_PINS 0x00000030 /* PH pins 5-4 */
#endif /* _ARM_ALLWINNER_AWIN_REG_H_ */
diff -r c8d6217e5dd3 -r 04d52637bb29 sys/arch/arm/allwinner/awin_twi.c
--- a/sys/arch/arm/allwinner/awin_twi.c Fri Dec 05 14:46:04 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_twi.c Fri Dec 05 15:25:27 2014 +0000
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.5 2014/11/23 13:39:58 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.6 2014/12/05 15:25:27 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -74,6 +74,14 @@
[3] = { 'B', AWIN_A31_PIO_PB_TWI3_FUNC, AWIN_A31_PIO_PB_TWI3_PINS },
};
+static const struct awin_gpio_pinset awin_twi_pinsets_a80[] = {
+ [0] = { 'H', AWIN_A80_PIO_PH_TWI0_FUNC, AWIN_A80_PIO_PH_TWI0_PINS },
+ [1] = { 'H', AWIN_A80_PIO_PH_TWI1_FUNC, AWIN_A80_PIO_PH_TWI1_PINS },
+ [2] = { 'H', AWIN_A80_PIO_PH_TWI2_FUNC, AWIN_A80_PIO_PH_TWI2_PINS },
+ [3] = { 'G', AWIN_A80_PIO_PG_TWI3_FUNC, AWIN_A80_PIO_PG_TWI3_PINS },
+ [4] = { 'B', AWIN_A80_PIO_PB_TWI4_FUNC, AWIN_A80_PIO_PB_TWI4_PINS },
+};
+
CFATTACH_DECL_NEW(awin_twi, sizeof(struct awin_twi_softc),
awin_twi_match, awin_twi_attach, NULL, NULL);
@@ -99,6 +107,9 @@
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
if (!awin_gpio_pinset_available(&awin_twi_pinsets_a31[port]))
return 0;
+ } else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ if (!awin_gpio_pinset_available(&awin_twi_pinsets_a80[port]))
+ return 0;
} else {
if (!awin_gpio_pinset_available(&awin_twi_pinsets[port]))
return 0;
@@ -124,6 +135,8 @@
*/
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
awin_gpio_pinset_acquire(&awin_twi_pinsets_a31[loc->loc_port]);
+ } else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ awin_gpio_pinset_acquire(&awin_twi_pinsets_a80[loc->loc_port]);
} else {
awin_gpio_pinset_acquire(&awin_twi_pinsets[loc->loc_port]);
}
@@ -131,12 +144,22 @@
/*
* Clock gating, soft reset
*/
- awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_APB1_GATING_REG, AWIN_APB_GATING1_TWI0 << loc->loc_port, 0);
- if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_REG,
+ AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI0 << loc->loc_port, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_A31_APB2_RESET_REG,
- AWIN_A31_APB2_RESET_TWI0_RST << loc->loc_port, 0);
+ AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_REG,
+ AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI0 << loc->loc_port, 0);
+ } else {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_APB1_GATING_REG,
+ AWIN_APB_GATING1_TWI0 << loc->loc_port, 0);
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A31_APB2_RESET_REG,
+ AWIN_A31_APB2_RESET_TWI0_RST << loc->loc_port, 0);
+ }
}
/*
@@ -146,10 +169,13 @@
loc->loc_offset, loc->loc_size, &bsh);
/*
- * A31 specific quirk
+ * A31/A80 quirk
*/
- if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ switch (awin_chip_id()) {
+ case AWIN_CHIP_ID_A31:
+ case AWIN_CHIP_ID_A80:
prop_dictionary_set_bool(cfg, "iflg-rwc", true);
+ break;
}
/*
diff -r c8d6217e5dd3 -r 04d52637bb29 sys/arch/evbarm/conf/ALLWINNER_A80
--- a/sys/arch/evbarm/conf/ALLWINNER_A80 Fri Dec 05 14:46:04 2014 +0000
+++ b/sys/arch/evbarm/conf/ALLWINNER_A80 Fri Dec 05 15:25:27 2014 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: ALLWINNER_A80,v 1.2 2014/12/05 14:36:44 jmcneill Exp $
+# $NetBSD: ALLWINNER_A80,v 1.3 2014/12/05 15:25:27 jmcneill Exp $
#
# ALLWINNER_A80 - Allwinner A80 boards (Cubieboard4, OptimusBoard, etc)
#
@@ -218,12 +218,14 @@
gpio* at awingpio?
# I2C Controllers
-#awiniic0 at awinio? port 0
-#iic0 at awiniic0
+awiniic0 at awinio? port 0
+iic0 at awiniic0
-#awiniic2 at awinio? port 2
-#iic2 at awiniic2
-#pcf8563rtc0 at iic2 addr 0x51 # PCF8563 RTC
+awiniic1 at awinio? port 1
+iic1 at awiniic1
+
+awiniic2 at awinio? port 2
+iic2 at awiniic2
# P2WI
#awinp2wi0 at awinio0
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