[src/trunk]: src/sys/arch Setting actlr.bit15=1 (Force in order issue in the ...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e2fff5acf9fe
branches:  trunk
changeset: 811178:e2fff5acf9fe
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Oct 15 07:13:50 2015 +0000

description:
Setting actlr.bit15=1 (Force in order issue in the branch execution unit)
makes my jetson tk1 stable.  Apply this workaround until we figure out
what the real problem is.

diffstat:

 sys/arch/arm/arm/cpufunc.c      |  15 +++++++++++++--
 sys/arch/arm/cortex/a9_mpsubr.S |   6 +++++-
 sys/arch/arm/include/armreg.h   |   7 ++++++-
 sys/arch/evbarm/conf/std.tegra  |   3 ++-
 4 files changed, 26 insertions(+), 5 deletions(-)

diffs (94 lines):

diff -r fe0b99a6115a -r e2fff5acf9fe sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Thu Oct 15 06:25:34 2015 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Thu Oct 15 07:13:50 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.156 2015/07/02 08:33:31 skrll Exp $      */
+/*     $NetBSD: cpufunc.c,v 1.157 2015/10/15 07:13:50 skrll Exp $      */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.156 2015/07/02 08:33:31 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.157 2015/10/15 07:13:50 skrll Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
@@ -3165,6 +3165,17 @@
                cpuctrl |= CPU_CONTROL_VECRELOC;
 #endif
 
+#ifdef TEGRAK1_PMAP_WORKAROUND
+       uint32_t auxctrl = armreg_auxctl_read();
+
+       // u-boot sets this incorrectly on boot cpu
+       auxctrl &= ~CORTEXA15_ACTLR_BTB;
+       auxctrl |= CORTEXA15_ACTLR_IOBEU;
+
+       /* Update auxctlr */
+       armreg_auxctl_write(auxctrl);
+#endif
+
        /* Clear out the cache */
        cpu_idcache_wbinv_all();
 
diff -r fe0b99a6115a -r e2fff5acf9fe sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S   Thu Oct 15 06:25:34 2015 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S   Thu Oct 15 07:13:50 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: a9_mpsubr.S,v 1.42 2015/06/09 08:08:14 skrll Exp $     */
+/*     $NetBSD: a9_mpsubr.S,v 1.43 2015/10/15 07:13:50 skrll Exp $     */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -498,6 +498,10 @@
        bfi     r0, r2, #31, #1                 // copy it to bit 31 in ACTRL
 #endif
 
+#if defined(TEGRAK1_PMAP_WORKAROUND)
+       orr     r0, r0, #CORTEXA15_ACTLR_IOBEU
+#endif
+
 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA9)
        //
        // Step 4a (continued on A5/A9), ACTLR.FW=1)
diff -r fe0b99a6115a -r e2fff5acf9fe sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Thu Oct 15 06:25:34 2015 +0000
+++ b/sys/arch/arm/include/armreg.h     Thu Oct 15 07:13:50 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.107 2015/06/09 08:08:14 skrll Exp $       */
+/*     $NetBSD: armreg.h,v 1.108 2015/10/15 07:13:50 skrll Exp $       */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -456,6 +456,11 @@
 #define        CORTEXA9_AUXCTL_ONEWAY  0x00000100 /* Allocate in on cache way only */
 #define        CORTEXA9_AUXCTL_PARITY  0x00000200 /* Support parity checking */
 
+/* Cortex-A15 Auxiliary Control Register (CP15 register 1, opcode 1) */
+#define        CORTEXA15_ACTLR_BTB     __BIT(0)  /* Cache and TLB updates broadcast */
+#define        CORTEXA15_ACTLR_SMP     __BIT(6)  /* SMP */
+#define        CORTEXA15_ACTLR_IOBEU   __BIT(15) /* In order issue in Branch Exec UNIT */
+
 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
 #define FC_DCACHE_REPL_LOCK    0x80000000 /* Replace DCache Lock */
 #define FC_DCACHE_STREAM_EN    0x20000000 /* DCache Streaming Switch */
diff -r fe0b99a6115a -r e2fff5acf9fe sys/arch/evbarm/conf/std.tegra
--- a/sys/arch/evbarm/conf/std.tegra    Thu Oct 15 06:25:34 2015 +0000
+++ b/sys/arch/evbarm/conf/std.tegra    Thu Oct 15 07:13:50 2015 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: std.tegra,v 1.7 2015/05/31 20:04:44 jmcneill Exp $
+#      $NetBSD: std.tegra,v 1.8 2015/10/15 07:13:50 skrll Exp $
 #
 
 machine        evbarm arm
@@ -19,6 +19,7 @@
 options        FPU_VFP
 options        PCI_NETBSD_CONFIGURE
 options        __HAVE_PCI_CONF_HOOK
+options        TEGRAK1_PMAP_WORKAROUND
 
 makeoptions    KERNEL_BASE_PHYS="0x81000000"
 makeoptions    KERNEL_BASE_VIRT="0x81000000"