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[src/trunk]: src/sys/dev/ic Make all of the COM_xxx type options runtime sele...
details: https://anonhg.NetBSD.org/src/rev/551fbb90ed86
branches: trunk
changeset: 827468:551fbb90ed86
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Oct 29 14:06:08 2017 +0000
description:
Make all of the COM_xxx type options runtime selectable. Kernel configs
with the existing options (COM_16650, COM_16750, COM_AWIN, COM_HAYESP, and
COM_PXA2X0) will select the correct type in com_attach_subr. New code
should specify the com type by passing COM_TYPE_xxx to comcnattach and/or
setting sc_type.
diffstat:
sys/dev/ic/com.c | 236 +++++++++++++++++++++++------------------------
sys/dev/ic/comreg.h | 10 +-
sys/dev/ic/comvar.h | 43 ++------
sys/dev/ic/ns16550reg.h | 19 +--
4 files changed, 139 insertions(+), 169 deletions(-)
diffs (truncated from 576 to 300 lines):
diff -r 64978e9e16cc -r 551fbb90ed86 sys/dev/ic/com.c
--- a/sys/dev/ic/com.c Sun Oct 29 11:38:43 2017 +0000
+++ b/sys/dev/ic/com.c Sun Oct 29 14:06:08 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: com.c,v 1.343 2017/10/28 04:53:55 riastradh Exp $ */
+/* $NetBSD: com.c,v 1.344 2017/10/29 14:06:08 jmcneill Exp $ */
/*-
* Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
@@ -66,7 +66,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.343 2017/10/28 04:53:55 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: com.c,v 1.344 2017/10/29 14:06:08 jmcneill Exp $");
#include "opt_com.h"
#include "opt_ddb.h"
@@ -122,9 +122,7 @@
#include <dev/ic/comvar.h>
#include <dev/ic/ns16550reg.h>
#include <dev/ic/st16650reg.h>
-#ifdef COM_HAYESP
#include <dev/ic/hayespreg.h>
-#endif
#define com_lcr com_cfcr
#include <dev/cons.h>
@@ -252,20 +250,12 @@
#ifdef COM_REGMAP
/* initializer for typical 16550-ish hardware */
-#define COM_REG_16550 { \
- com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \
- com_efr, com_lcr, com_mcr, com_lsr, com_msr }
-/* 16750-specific register set, additional UART status register */
-#define COM_REG_16750 { \
+#define COM_REG_STD { \
com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \
com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr }
-#ifdef COM_16750
-const bus_size_t com_std_map[32] = COM_REG_16750;
-#else
-const bus_size_t com_std_map[16] = COM_REG_16550;
-#endif /* COM_16750 */
+const bus_size_t com_std_map[32] = COM_REG_STD;
#endif /* COM_REGMAP */
#define COMDIALOUT_MASK TTDIALOUT_MASK
@@ -393,9 +383,7 @@
{
struct com_regs *regsp = &sc->sc_regs;
struct tty *tp;
-#if defined(COM_16650) || defined(COM_16750)
u_int8_t lcr;
-#endif
const char *fifo_msg = NULL;
prop_dictionary_t dict;
bool is_console = true;
@@ -407,6 +395,18 @@
callout_init(&sc->sc_diag_callout, 0);
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
+#if defined(COM_16650)
+ sc->sc_type = COM_TYPE_16650;
+#elif defined(COM_16750)
+ sc->sc_type = COM_TYPE_16750;
+#elif defined(COM_AWIN)
+ sc->sc_type = COM_TYPE_SUNXI;
+#elif defined(COM_HAYESP)
+ sc->sc_type = COM_TYPE_HAYESP;
+#elif defined(COM_PXA2X0)
+ sc->sc_type = COM_TYPE_PXA2x0;
+#endif
+
/* Disable interrupts before configuring the device. */
if (sc->sc_type == COM_TYPE_PXA2x0)
sc->sc_ier = IER_EUART;
@@ -424,10 +424,13 @@
(u_long)comcons_info.regs.cr_iobase);
}
-#if defined(COM_16750) || defined(COM_AWIN)
- /* Use in comintr(). */
- sc->sc_lcr = cflag2lcr(comcons_info.cflag);
-#endif
+ switch (sc->sc_type) {
+ case COM_TYPE_16750:
+ case COM_TYPE_SUNXI:
+ /* Use in comintr(). */
+ sc->sc_lcr = cflag2lcr(comcons_info.cflag);
+ break;
+ }
/* Make sure the console is always "hardwired". */
delay(10000); /* wait for output to finish */
@@ -501,7 +504,8 @@
== FIFO_TRIGGER_14) {
SET(sc->sc_hwflags, COM_HW_FIFO);
-#ifdef COM_16650
+ fifo_msg = "ns16550a, working fifo";
+
/*
* IIR changes into the EFR if LCR is set to LCR_EERS
* on 16650s. We also know IIR != 0 at this point.
@@ -513,23 +517,32 @@
* setting DLAB enable gives access to the EFR on
* these chips.
*/
- lcr = CSR_READ_1(regsp, COM_REG_LCR);
- CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
- CSR_WRITE_1(regsp, COM_REG_EFR, 0);
- if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
+ if (sc->sc_type == COM_TYPE_16650) {
+ lcr = CSR_READ_1(regsp, COM_REG_LCR);
+ CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
+ CSR_WRITE_1(regsp, COM_REG_EFR, 0);
if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
- CLR(sc->sc_hwflags, COM_HW_FIFO);
- sc->sc_fifolen = 0;
- } else {
- SET(sc->sc_hwflags, COM_HW_FLOW);
- sc->sc_fifolen = 32;
- }
- } else
-#endif
- sc->sc_fifolen = 16;
-
-#ifdef COM_16750
+ CSR_WRITE_1(regsp, COM_REG_LCR,
+ lcr | LCR_DLAB);
+ if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
+ CLR(sc->sc_hwflags, COM_HW_FIFO);
+ sc->sc_fifolen = 0;
+ } else {
+ SET(sc->sc_hwflags, COM_HW_FLOW);
+ sc->sc_fifolen = 32;
+ }
+ } else
+ sc->sc_fifolen = 16;
+
+ CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
+ if (sc->sc_fifolen == 0)
+ fifo_msg = "st16650, broken fifo";
+ else if (sc->sc_fifolen == 32)
+ fifo_msg = "st16650a, working fifo";
+ else
+ fifo_msg = "ns16550a, working fifo";
+ }
+
/*
* TL16C750 can enable 64byte FIFO, only when DLAB
* is 1. However, some 16750 may always enable. For
@@ -539,54 +552,43 @@
* use SC16C750. Probably 32 bytes of FIFO and HW FLOW
* should become effective.
*/
- uint8_t iir1, iir2;
- uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14;
-
- if (sc->sc_type == COM_TYPE_INGENIC)
- fcr |= FIFO_UART_ON;
-
- lcr = CSR_READ_1(regsp, COM_REG_LCR);
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB);
- CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE);
- iir1 = CSR_READ_1(regsp, COM_REG_IIR);
- CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
- CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE);
- iir2 = CSR_READ_1(regsp, COM_REG_IIR);
-
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
-
- if (!ISSET(iir1, IIR_64B_FIFO) &&
- ISSET(iir2, IIR_64B_FIFO)) {
- /* It is TL16C750. */
- sc->sc_fifolen = 64;
- SET(sc->sc_hwflags, COM_HW_AFE);
- } else
+ if (sc->sc_type == COM_TYPE_16750) {
+ uint8_t iir1, iir2;
+ uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14;
+
+ lcr = CSR_READ_1(regsp, COM_REG_LCR);
+ CSR_WRITE_1(regsp, COM_REG_LCR,
+ lcr & ~LCR_DLAB);
+ CSR_WRITE_1(regsp, COM_REG_FIFO,
+ fcr | FIFO_64B_ENABLE);
+ iir1 = CSR_READ_1(regsp, COM_REG_IIR);
CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
-#endif
-
-#ifdef COM_16650
- CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
- if (sc->sc_fifolen == 0)
- fifo_msg = "st16650, broken fifo";
- else if (sc->sc_fifolen == 32)
- fifo_msg = "st16650a, working fifo";
- else
-#endif
-#ifdef COM_16750
- if (sc->sc_fifolen == 64)
- fifo_msg = "tl16c750, working fifo";
- else
-#endif
- fifo_msg = "ns16550a, working fifo";
+ CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
+ CSR_WRITE_1(regsp, COM_REG_FIFO,
+ fcr | FIFO_64B_ENABLE);
+ iir2 = CSR_READ_1(regsp, COM_REG_IIR);
+
+ CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
+
+ if (!ISSET(iir1, IIR_64B_FIFO) &&
+ ISSET(iir2, IIR_64B_FIFO)) {
+ /* It is TL16C750. */
+ sc->sc_fifolen = 64;
+ SET(sc->sc_hwflags, COM_HW_AFE);
+ } else
+ CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
+
+ if (sc->sc_fifolen == 64)
+ fifo_msg = "tl16c750, working fifo";
+ else
+ fifo_msg = "ns16750, working fifo";
+ }
} else
fifo_msg = "ns16550, broken fifo";
else
fifo_msg = "ns8250 or ns16450, no fifo";
- if (sc->sc_type == COM_TYPE_INGENIC) {
- CSR_WRITE_1(regsp, COM_REG_FIFO, FIFO_UART_ON);
- } else
- CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
+ CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
+
fifodelay:
/*
* Some chips will clear down both Tx and Rx FIFOs when zero is
@@ -685,7 +687,6 @@
CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
(void) CSR_READ_1(regsp, COM_REG_IIR);
-#ifdef COM_HAYESP
/* Look for a Hayes ESP board. */
if (sc->sc_type == COM_TYPE_HAYESP) {
@@ -716,7 +717,6 @@
bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
HAYESP_LOBYTE(HAYESP_RXLOWMARK));
}
-#endif
if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB))
com_enable_debugport(sc);
@@ -1360,7 +1360,6 @@
if (COM_ISALIVE(sc) == 0)
return (EIO);
-#ifdef COM_HAYESP
if (sc->sc_type == COM_TYPE_HAYESP) {
int prescaler, speed;
@@ -1378,8 +1377,7 @@
return (EINVAL);
sc->sc_prescaler = prescaler;
} else
-#endif
- ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type);
+ ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type);
/* Check requested parameters. */
if (ospeed < 0)
@@ -1565,6 +1563,7 @@
com_iflush(struct com_softc *sc)
{
struct com_regs *regsp = &sc->sc_regs;
+ uint8_t fifo;
#ifdef DIAGNOSTIC
int reg;
#endif
@@ -1588,19 +1587,21 @@
aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg);
#endif
-#if defined(COM_16750) || defined(COM_AWIN)
- uint8_t fifo;
- /*
- * Reset all Rx/Tx FIFO, preserve current FIFO length.
- * This should prevent triggering busy interrupt while
- * manipulating divisors.
- */
- fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
- FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14);
- CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST |
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