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[src/trunk]: src/sys/arch/arm/sunxi Add A83T clock IDs.
details: https://anonhg.NetBSD.org/src/rev/7255ee2b173e
branches: trunk
changeset: 827438:7255ee2b173e
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Oct 28 12:07:40 2017 +0000
description:
Add A83T clock IDs.
diffstat:
sys/arch/arm/sunxi/sun8i_a83t_ccu.c | 175 ++++++++++++++---------------------
sys/arch/arm/sunxi/sun8i_a83t_ccu.h | 150 ++++++++++++++++++++++++++++++-
2 files changed, 217 insertions(+), 108 deletions(-)
diffs (truncated from 440 to 300 lines):
diff -r 1f00f3217125 -r 7255ee2b173e sys/arch/arm/sunxi/sun8i_a83t_ccu.c
--- a/sys/arch/arm/sunxi/sun8i_a83t_ccu.c Sat Oct 28 10:54:18 2017 +0000
+++ b/sys/arch/arm/sunxi/sun8i_a83t_ccu.c Sat Oct 28 12:07:40 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun8i_a83t_ccu.c,v 1.1 2017/07/06 22:10:14 jmcneill Exp $ */
+/* $NetBSD: sun8i_a83t_ccu.c,v 1.2 2017/10/28 12:07:40 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: sun8i_a83t_ccu.c,v 1.1 2017/07/06 22:10:14 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun8i_a83t_ccu.c,v 1.2 2017/10/28 12:07:40 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -41,7 +41,7 @@
#include <arm/sunxi/sunxi_ccu.h>
#include <arm/sunxi/sun8i_a83t_ccu.h>
-#define PLL_PERIPH0_CTRL_REG 0x028
+#define PLL_PERIPH_CTRL_REG 0x028
#define AHB1_APB1_CFG_REG 0x054
#define APB2_CFG_REG 0x058
#define BUS_CLK_GATING_REG0 0x060
@@ -70,66 +70,49 @@
sun8i_a83t_ccu_match, sun8i_a83t_ccu_attach, NULL, NULL);
static struct sunxi_ccu_reset sun8i_a83t_ccu_resets[] = {
- SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0),
- SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1),
- SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2),
- SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3),
+ SUNXI_CCU_RESET(A83T_RST_USB_PHY0, USBPHY_CFG_REG, 0),
+ SUNXI_CCU_RESET(A83T_RST_USB_PHY1, USBPHY_CFG_REG, 1),
- SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31),
+ SUNXI_CCU_RESET(A83T_RST_MBUS, MBUS_RST_REG, 31),
- SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
- SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
- SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
- SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
- SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
- SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13),
- SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
- SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
- SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
- SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
- SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
- SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
- SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23),
- SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24),
- SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25),
- SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26),
- SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27),
- SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28),
- SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29),
- SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30),
- SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31),
+ SUNXI_CCU_RESET(A83T_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
+ SUNXI_CCU_RESET(A83T_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
+ SUNXI_CCU_RESET(A83T_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
+ SUNXI_CCU_RESET(A83T_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
+ SUNXI_CCU_RESET(A83T_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13),
+ SUNXI_CCU_RESET(A83T_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
+ SUNXI_CCU_RESET(A83T_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
+ SUNXI_CCU_RESET(A83T_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
+ SUNXI_CCU_RESET(A83T_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
+ SUNXI_CCU_RESET(A83T_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
+ SUNXI_CCU_RESET(A83T_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23),
+ SUNXI_CCU_RESET(A83T_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24),
+ SUNXI_CCU_RESET(A83T_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25),
+ SUNXI_CCU_RESET(A83T_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28),
- SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
- SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3),
- SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4),
- SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5),
- SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
- SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9),
- SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10),
- SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11),
- SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
- SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20),
- SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
- SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
- SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31),
-
- SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2),
+ SUNXI_CCU_RESET(A83T_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
+ SUNXI_CCU_RESET(A83T_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3),
+ SUNXI_CCU_RESET(A83T_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4),
+ SUNXI_CCU_RESET(A83T_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
+ SUNXI_CCU_RESET(A83T_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10),
+ SUNXI_CCU_RESET(A83T_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11),
+ SUNXI_CCU_RESET(A83T_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
+ SUNXI_CCU_RESET(A83T_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20),
+ SUNXI_CCU_RESET(A83T_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
+ SUNXI_CCU_RESET(A83T_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
- SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0),
- SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1),
- SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8),
- SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12),
- SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13),
- SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14),
+ SUNXI_CCU_RESET(A83T_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1),
+ SUNXI_CCU_RESET(A83T_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12),
+ SUNXI_CCU_RESET(A83T_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13),
+ SUNXI_CCU_RESET(A83T_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14),
- SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
- SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
- SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
- SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
- SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
- SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
- SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
- SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20),
+ SUNXI_CCU_RESET(A83T_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
+ SUNXI_CCU_RESET(A83T_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
+ SUNXI_CCU_RESET(A83T_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
+ SUNXI_CCU_RESET(A83T_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
+ SUNXI_CCU_RESET(A83T_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
+ SUNXI_CCU_RESET(A83T_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
+ SUNXI_CCU_RESET(A83T_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
};
static const char *ahb1_parents[] = { "losc", "hosc", "pll_periph" };
@@ -139,8 +122,8 @@
static const char *mod_parents[] = { "hosc", "pll_periph" };
static struct sunxi_ccu_clk sun8i_a83t_ccu_clks[] = {
- SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph", "hosc",
- PLL_PERIPH0_CTRL_REG, /* reg */
+ SUNXI_CCU_NKMP(A83T_CLK_PLL_PERIPH, "pll_periph", "hosc",
+ PLL_PERIPH_CTRL_REG, /* reg */
__BITS(15,8), /* n */
0, /* k */
__BIT(18), /* m */
@@ -148,7 +131,7 @@
__BIT(31), /* enable */
SUNXI_CCU_NKMP_FACTOR_N_EXACT),
- SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents,
+ SUNXI_CCU_PREDIV(A83T_CLK_AHB1, "ahb1", ahb1_parents,
AHB1_APB1_CFG_REG, /* reg */
__BITS(7,6), /* prediv */
__BIT(3), /* prediv_sel */
@@ -156,7 +139,7 @@
__BITS(13,12), /* sel */
SUNXI_CCU_PREDIV_POWER_OF_TWO),
- SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents,
+ SUNXI_CCU_PREDIV(A83T_CLK_AHB2, "ahb2", ahb2_parents,
APB2_CFG_REG, /* reg */
0, /* prediv */
__BIT(1), /* prediv_sel */
@@ -164,13 +147,13 @@
__BITS(1,0), /* sel */
SUNXI_CCU_PREDIV_DIVIDE_BY_TWO),
- SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents,
+ SUNXI_CCU_DIV(A83T_CLK_APB1, "apb1", apb1_parents,
AHB1_APB1_CFG_REG, /* reg */
__BITS(9,8), /* div */
0, /* sel */
SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE),
- SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents,
+ SUNXI_CCU_NM(A83T_CLK_APB2, "apb2", apb2_parents,
APB2_CFG_REG, /* reg */
__BITS(17,16), /* n */
__BITS(4,0), /* m */
@@ -178,77 +161,57 @@
0, /* enable */
SUNXI_CCU_NM_POWER_OF_TWO),
- SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents,
+ SUNXI_CCU_NM(A83T_CLK_MMC0, "mmc0", mod_parents,
SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
- SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents,
+ SUNXI_CCU_NM(A83T_CLK_MMC1, "mmc1", mod_parents,
SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
- SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents,
+ SUNXI_CCU_NM(A83T_CLK_MMC2, "mmc2", mod_parents,
SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
- SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
BUS_CLK_GATING_REG0, 8),
- SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
BUS_CLK_GATING_REG0, 9),
- SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
BUS_CLK_GATING_REG0, 10),
- SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_EMAC, "bus-emac", "ahb2",
BUS_CLK_GATING_REG0, 17),
- SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_OTG, "bus-otg", "ahb1",
BUS_CLK_GATING_REG0, 23),
- SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI0, "bus-ehci0", "ahb1",
BUS_CLK_GATING_REG0, 24),
- SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_EHCI1, "bus-ehci1", "ahb2",
BUS_CLK_GATING_REG0, 25),
- SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2",
- BUS_CLK_GATING_REG0, 26),
- SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2",
- BUS_CLK_GATING_REG0, 27),
- SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_OHCI0, "bus-ohci0", "ahb1",
BUS_CLK_GATING_REG0, 28),
- SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2",
- BUS_CLK_GATING_REG0, 29),
- SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2",
- BUS_CLK_GATING_REG0, 30),
- SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2",
- BUS_CLK_GATING_REG0, 31),
- SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_PIO, "bus-pio", "apb1",
BUS_CLK_GATING_REG2, 5),
- SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_I2C0, "bus-i2c0", "apb2",
BUS_CLK_GATING_REG3, 0),
- SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_I2C1, "bus-i2c1", "apb2",
BUS_CLK_GATING_REG3, 1),
- SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_I2C2, "bus-i2c2", "apb2",
BUS_CLK_GATING_REG3, 2),
- SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_UART0, "bus-uart0", "apb2",
BUS_CLK_GATING_REG3, 16),
- SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_UART1, "bus-uart1", "apb2",
BUS_CLK_GATING_REG3, 17),
- SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_UART2, "bus-uart2", "apb2",
BUS_CLK_GATING_REG3, 18),
- SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2",
+ SUNXI_CCU_GATE(A83T_CLK_BUS_UART3, "bus-uart3", "apb2",
BUS_CLK_GATING_REG3, 19),
- SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc",
+ SUNXI_CCU_GATE(A83T_CLK_USB_PHY0, "usb-phy0", "hosc",
USBPHY_CFG_REG, 8),
- SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc",
+ SUNXI_CCU_GATE(A83T_CLK_USB_PHY1, "usb-phy1", "hosc",
USBPHY_CFG_REG, 9),
- SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc",
- USBPHY_CFG_REG, 10),
- SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc",
- USBPHY_CFG_REG, 11),
- SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc",
+ SUNXI_CCU_GATE(A83T_CLK_USB_OHCI0, "usb-ohci0", "hosc",
USBPHY_CFG_REG, 16),
- SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc",
- USBPHY_CFG_REG, 17),
- SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc",
- USBPHY_CFG_REG, 18),
- SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc",
- USBPHY_CFG_REG, 19),
};
static int
diff -r 1f00f3217125 -r 7255ee2b173e sys/arch/arm/sunxi/sun8i_a83t_ccu.h
--- a/sys/arch/arm/sunxi/sun8i_a83t_ccu.h Sat Oct 28 10:54:18 2017 +0000
+++ b/sys/arch/arm/sunxi/sun8i_a83t_ccu.h Sat Oct 28 12:07:40 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun8i_a83t_ccu.h,v 1.1 2017/07/06 22:10:14 jmcneill Exp $ */
+/* $NetBSD: sun8i_a83t_ccu.h,v 1.2 2017/10/28 12:07:40 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -29,6 +29,152 @@
#ifndef _SUN8I_A83T_CCU_H
#define _SUN8I_A83T_CCU_H
-#include <arm/sunxi/sun8i_h3_ccu.h>
+#define A83T_RST_USB_PHY0 0
+#define A83T_RST_USB_PHY1 1
+#define A83T_RST_USB_HSIC 2
+#define A83T_RST_DRAM 3
+#define A83T_RST_MBUS 4
+#define A83T_RST_BUS_MIPI_DSI 5
+#define A83T_RST_BUS_SS 6
+#define A83T_RST_BUS_DMA 7
+#define A83T_RST_BUS_MMC0 8
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