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[src/trunk]: src/sys/arch/arm/nvidia #define<tab>
details: https://anonhg.NetBSD.org/src/rev/074369d56c12
branches: trunk
changeset: 826695:074369d56c12
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Sep 22 10:55:43 2017 +0000
description:
#define<tab>
diffstat:
sys/arch/arm/nvidia/tegra210_carreg.h | 928 +++++++++++++++++-----------------
1 files changed, 464 insertions(+), 464 deletions(-)
diffs (truncated from 1014 to 300 lines):
diff -r 3d3e8a6bbd05 -r 074369d56c12 sys/arch/arm/nvidia/tegra210_carreg.h
--- a/sys/arch/arm/nvidia/tegra210_carreg.h Fri Sep 22 10:54:44 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_carreg.h Fri Sep 22 10:55:43 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_carreg.h,v 1.4 2017/09/22 10:54:44 jmcneill Exp $ */
+/* $NetBSD: tegra210_carreg.h,v 1.5 2017/09/22 10:55:43 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -29,18 +29,18 @@
#ifndef _ARM_TEGRA210_CARREG_H
#define _ARM_TEGRA210_CARREG_H
-#define TEGRA210_REF_FREQ 38400000
+#define TEGRA210_REF_FREQ 38400000
-#define CAR_RST_SOURCE_REG 0x00
-#define CAR_RST_SOURCE_WDT_EN __BIT(5)
-#define CAR_RST_SOURCE_WDT_SEL __BIT(4)
-#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2)
-#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1)
-#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0)
+#define CAR_RST_SOURCE_REG 0x00
+#define CAR_RST_SOURCE_WDT_EN __BIT(5)
+#define CAR_RST_SOURCE_WDT_SEL __BIT(4)
+#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2)
+#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1)
+#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0)
-#define CAR_CLK_OUT_ENB_L_REG 0x10
-#define CAR_CLK_OUT_ENB_H_REG 0x14
-#define CAR_CLK_OUT_ENB_U_REG 0x18
+#define CAR_CLK_OUT_ENB_L_REG 0x10
+#define CAR_CLK_OUT_ENB_H_REG 0x14
+#define CAR_CLK_OUT_ENB_U_REG 0x18
#define CAR_PLLE_SS_CNTL_REG 0x68
#define CAR_PLLE_SS_CNTL_INTEGOFFSET __BITS(31,30)
@@ -54,60 +54,60 @@
#define CAR_PLLE_SS_CNTL_BYPASS_SS __BIT(10)
#define CAR_PLLE_SS_CNTL_SSCMAX __BITS(8,0)
-#define CAR_PLLP_BASE_REG 0xa0
-#define CAR_PLLP_BASE_BYPASS __BIT(31)
-#define CAR_PLLP_BASE_ENABLE __BIT(30)
-#define CAR_PLLP_BASE_REF_DIS __BIT(29)
-#define CAR_PLLP_BASE_OVERRIDE __BIT(28)
-#define CAR_PLLP_BASE_LOCK __BIT(27)
-#define CAR_PLLP_BASE_DIVP __BITS(24,20)
-#define CAR_PLLP_BASE_DIVN __BITS(17,10)
-#define CAR_PLLP_BASE_DIVM __BITS(7,0)
+#define CAR_PLLP_BASE_REG 0xa0
+#define CAR_PLLP_BASE_BYPASS __BIT(31)
+#define CAR_PLLP_BASE_ENABLE __BIT(30)
+#define CAR_PLLP_BASE_REF_DIS __BIT(29)
+#define CAR_PLLP_BASE_OVERRIDE __BIT(28)
+#define CAR_PLLP_BASE_LOCK __BIT(27)
+#define CAR_PLLP_BASE_DIVP __BITS(24,20)
+#define CAR_PLLP_BASE_DIVN __BITS(17,10)
+#define CAR_PLLP_BASE_DIVM __BITS(7,0)
-#define CAR_PLLP_OUTA_REG 0xa4
-#define CAR_PLLP_OUTA_OUT1_RATIO __BITS(15,8)
-#define CAR_PLLP_OUTA_OUT1_OVRRIDE __BIT(2)
-#define CAR_PLLP_OUTA_OUT1_CLKEN __BIT(1)
-#define CAR_PLLP_OUTA_OUT1_RSTN __BIT(0)
-#define CAR_PLLP_OUTB_REG 0xa8
-#define CAR_PLLP_OUTB_OUT4_RATIO __BITS(31,24)
-#define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18)
-#define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17)
-#define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16)
-#define CAR_PLLP_OUTB_OUT3_RATIO __BITS(15,8)
-#define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2)
-#define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1)
-#define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0)
-#define CAR_PLLP_OUTC_REG 0x67c
-#define CAR_PLLP_OUTC_OUT5_RATIO __BITS(31,24)
-#define CAR_PLLP_OUTC_OUT5_OVERRIDE __BIT(18)
-#define CAR_PLLP_OUTC_OUT5_CLKEN __BIT(17)
-#define CAR_PLLP_OUTC_OUT5_RSTN __BIT(16)
-#define CAR_PLLP_MISC_REG 0xac
+#define CAR_PLLP_OUTA_REG 0xa4
+#define CAR_PLLP_OUTA_OUT1_RATIO __BITS(15,8)
+#define CAR_PLLP_OUTA_OUT1_OVRRIDE __BIT(2)
+#define CAR_PLLP_OUTA_OUT1_CLKEN __BIT(1)
+#define CAR_PLLP_OUTA_OUT1_RSTN __BIT(0)
+#define CAR_PLLP_OUTB_REG 0xa8
+#define CAR_PLLP_OUTB_OUT4_RATIO __BITS(31,24)
+#define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18)
+#define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17)
+#define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16)
+#define CAR_PLLP_OUTB_OUT3_RATIO __BITS(15,8)
+#define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2)
+#define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1)
+#define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0)
+#define CAR_PLLP_OUTC_REG 0x67c
+#define CAR_PLLP_OUTC_OUT5_RATIO __BITS(31,24)
+#define CAR_PLLP_OUTC_OUT5_OVERRIDE __BIT(18)
+#define CAR_PLLP_OUTC_OUT5_CLKEN __BIT(17)
+#define CAR_PLLP_OUTC_OUT5_RSTN __BIT(16)
+#define CAR_PLLP_MISC_REG 0xac
-#define CAR_PLLC_BASE_REG 0x80
-#define CAR_PLLC_BASE_BYPASS __BIT(31)
-#define CAR_PLLC_BASE_ENABLE __BIT(30)
-#define CAR_PLLC_BASE_REF_DIS __BIT(29)
-#define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(27)
-#define CAR_PLLC_BASE_LOCK __BIT(26)
-#define CAR_PLLC_BASE_DIVP __BITS(24,20)
-#define CAR_PLLC_BASE_DIVN __BITS(17,10)
-#define CAR_PLLC_BASE_DIVM __BITS(7,0)
+#define CAR_PLLC_BASE_REG 0x80
+#define CAR_PLLC_BASE_BYPASS __BIT(31)
+#define CAR_PLLC_BASE_ENABLE __BIT(30)
+#define CAR_PLLC_BASE_REF_DIS __BIT(29)
+#define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(27)
+#define CAR_PLLC_BASE_LOCK __BIT(26)
+#define CAR_PLLC_BASE_DIVP __BITS(24,20)
+#define CAR_PLLC_BASE_DIVN __BITS(17,10)
+#define CAR_PLLC_BASE_DIVM __BITS(7,0)
-#define CAR_PLLU_BASE_REG 0xc0
-#define CAR_PLLU_BASE_BYPASS __BIT(31)
-#define CAR_PLLU_BASE_ENABLE __BIT(30)
-#define CAR_PLLU_BASE_REF_DIS __BIT(29)
-#define CAR_PLLU_BASE_LOCK __BIT(27)
-#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25)
-#define CAR_PLLU_BASE_OVERRIDE __BIT(24)
-#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23)
-#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22)
-#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21)
-#define CAR_PLLU_BASE_DIVP __BITS(20,16)
-#define CAR_PLLU_BASE_DIVN __BITS(15,8)
-#define CAR_PLLU_BASE_DIVM __BITS(4,0)
+#define CAR_PLLU_BASE_REG 0xc0
+#define CAR_PLLU_BASE_BYPASS __BIT(31)
+#define CAR_PLLU_BASE_ENABLE __BIT(30)
+#define CAR_PLLU_BASE_REF_DIS __BIT(29)
+#define CAR_PLLU_BASE_LOCK __BIT(27)
+#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25)
+#define CAR_PLLU_BASE_OVERRIDE __BIT(24)
+#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23)
+#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22)
+#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21)
+#define CAR_PLLU_BASE_DIVP __BITS(20,16)
+#define CAR_PLLU_BASE_DIVN __BITS(15,8)
+#define CAR_PLLU_BASE_DIVM __BITS(4,0)
#define CAR_PLLU_OUTA_REG 0xc4
#define CAR_PLLU_OUTA_OUT2_RATIO __BITS(31,24)
@@ -128,315 +128,315 @@
#define CAR_PLLU_MISC_KVCO __BIT(24)
#define CAR_PLLU_MISC_SETUP __BITS(23,0)
-#define CAR_PLLD_BASE_REG 0xd0
-#define CAR_PLLD_BASE_BYPASS __BIT(31)
-#define CAR_PLLD_BASE_ENABLE __BIT(30)
-#define CAR_PLLD_BASE_REF_DIS __BIT(29)
-#define CAR_PLLD_BASE_LOCK __BIT(27)
-#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25)
-#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23)
-#define CAR_PLLD_BASE_DIVP __BITS(22,20)
-#define CAR_PLLD_BASE_DIVN __BITS(18,11)
-#define CAR_PLLD_BASE_DIVM __BITS(7,0)
+#define CAR_PLLD_BASE_REG 0xd0
+#define CAR_PLLD_BASE_BYPASS __BIT(31)
+#define CAR_PLLD_BASE_ENABLE __BIT(30)
+#define CAR_PLLD_BASE_REF_DIS __BIT(29)
+#define CAR_PLLD_BASE_LOCK __BIT(27)
+#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25)
+#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23)
+#define CAR_PLLD_BASE_DIVP __BITS(22,20)
+#define CAR_PLLD_BASE_DIVN __BITS(18,11)
+#define CAR_PLLD_BASE_DIVM __BITS(7,0)
-#define CAR_PLLD_MISC_REG 0xdc
+#define CAR_PLLD_MISC_REG 0xdc
-#define CAR_PLLX_BASE_REG 0xe0
-#define CAR_PLLX_BASE_BYPASS __BIT(31)
-#define CAR_PLLX_BASE_ENABLE __BIT(30)
-#define CAR_PLLX_BASE_REF_DIS __BIT(29)
-#define CAR_PLLX_BASE_LOCK __BIT(27)
-#define CAR_PLLX_BASE_DIVP __BITS(24,20)
-#define CAR_PLLX_BASE_DIVN __BITS(15,8)
-#define CAR_PLLX_BASE_DIVM __BITS(7,0)
+#define CAR_PLLX_BASE_REG 0xe0
+#define CAR_PLLX_BASE_BYPASS __BIT(31)
+#define CAR_PLLX_BASE_ENABLE __BIT(30)
+#define CAR_PLLX_BASE_REF_DIS __BIT(29)
+#define CAR_PLLX_BASE_LOCK __BIT(27)
+#define CAR_PLLX_BASE_DIVP __BITS(24,20)
+#define CAR_PLLX_BASE_DIVN __BITS(15,8)
+#define CAR_PLLX_BASE_DIVM __BITS(7,0)
-#define CAR_PLLX_MISC_REG 0xe4
-#define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28)
-#define CAR_PLLX_MISC_PTS __BITS(23,22)
-#define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18)
+#define CAR_PLLX_MISC_REG 0xe4
+#define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28)
+#define CAR_PLLX_MISC_PTS __BITS(23,22)
+#define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18)
-#define CAR_PLLE_BASE_REG 0xe8
-#define CAR_PLLE_BASE_ENABLE __BIT(31)
-#define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(30)
-#define CAR_PLLE_BASE_FDIV4B __BIT(29)
-#define CAR_PLLE_BASE_DIVP_CML __BITS(28,24)
-#define CAR_PLLE_BASE_EXT_SETUP_23_16 __BITS(23,16)
-#define CAR_PLLE_BASE_DIVN __BITS(15,8)
-#define CAR_PLLE_BASE_DIVM __BITS(7,0)
+#define CAR_PLLE_BASE_REG 0xe8
+#define CAR_PLLE_BASE_ENABLE __BIT(31)
+#define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(30)
+#define CAR_PLLE_BASE_FDIV4B __BIT(29)
+#define CAR_PLLE_BASE_DIVP_CML __BITS(28,24)
+#define CAR_PLLE_BASE_EXT_SETUP_23_16 __BITS(23,16)
+#define CAR_PLLE_BASE_DIVN __BITS(15,8)
+#define CAR_PLLE_BASE_DIVM __BITS(7,0)
-#define CAR_PLLE_MISC_REG 0xec
-#define CAR_PLLE_MISC_SETUP __BITS(31,16)
-#define CAR_PLLE_MISC_ENABLE __BIT(15)
-#define CAR_PLLE_MISC_IDDQ_SWCTL __BIT(14)
-#define CAR_PLLE_MISC_IDDQ_OVERRIDE __BIT(13)
-#define CAR_PLLE_MISC_LOCK __BIT(11)
-#define CAR_PLLE_MISC_LOCK_ENABLE __BIT(9)
+#define CAR_PLLE_MISC_REG 0xec
+#define CAR_PLLE_MISC_SETUP __BITS(31,16)
+#define CAR_PLLE_MISC_ENABLE __BIT(15)
+#define CAR_PLLE_MISC_IDDQ_SWCTL __BIT(14)
+#define CAR_PLLE_MISC_IDDQ_OVERRIDE __BIT(13)
+#define CAR_PLLE_MISC_LOCK __BIT(11)
+#define CAR_PLLE_MISC_LOCK_ENABLE __BIT(9)
#define CAR_PLLE_MISC_PTS __BIT(8)
-#define CAR_PLLD2_BASE_REG 0x4b8
-#define CAR_PLLD2_BASE_BYPASS __BIT(31)
-#define CAR_PLLD2_BASE_ENABLE __BIT(30)
-#define CAR_PLLD2_BASE_REF_DIS __BIT(29)
-#define CAR_PLLD2_BASE_FREQLOCK __BIT(28)
-#define CAR_PLLD2_BASE_LOCK __BIT(27)
-#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25)
-#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D 0
-#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2 1
-#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24)
-#define CAR_PLLD2_BASE_DIVP __BITS(23,19)
-#define CAR_PLLD2_BASE_IDDQ __BIT(18)
-#define CAR_PLLD2_BASE_PTS __BIT(16)
-#define CAR_PLLD2_BASE_DIVN __BITS(15,8)
-#define CAR_PLLD2_BASE_DIVM __BITS(7,0)
+#define CAR_PLLD2_BASE_REG 0x4b8
+#define CAR_PLLD2_BASE_BYPASS __BIT(31)
+#define CAR_PLLD2_BASE_ENABLE __BIT(30)
+#define CAR_PLLD2_BASE_REF_DIS __BIT(29)
+#define CAR_PLLD2_BASE_FREQLOCK __BIT(28)
+#define CAR_PLLD2_BASE_LOCK __BIT(27)
+#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25)
+#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D 0
+#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2 1
+#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24)
+#define CAR_PLLD2_BASE_DIVP __BITS(23,19)
+#define CAR_PLLD2_BASE_IDDQ __BIT(18)
+#define CAR_PLLD2_BASE_PTS __BIT(16)
+#define CAR_PLLD2_BASE_DIVN __BITS(15,8)
+#define CAR_PLLD2_BASE_DIVM __BITS(7,0)
-#define CAR_PLLD2_MISC_REG 0x4bc
-#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30)
-#define CAR_PLLD2_MISC_KCP __BITS(26,25)
-#define CAR_PLLD2_MISC_KVCO __BIT(24)
-#define CAR_PLLD2_MISC_SETUP __BITS(23,0)
+#define CAR_PLLD2_MISC_REG 0x4bc
+#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30)
+#define CAR_PLLD2_MISC_KCP __BITS(26,25)
+#define CAR_PLLD2_MISC_KVCO __BIT(24)
+#define CAR_PLLD2_MISC_SETUP __BITS(23,0)
-#define CAR_CLKSRC_I2C1_REG 0x124
-#define CAR_CLKSRC_I2C2_REG 0x198
-#define CAR_CLKSRC_I2C3_REG 0x1b8
-#define CAR_CLKSRC_I2C4_REG 0x3c4
-#define CAR_CLKSRC_I2C5_REG 0x128
-#define CAR_CLKSRC_I2C6_REG 0x65c
+#define CAR_CLKSRC_I2C1_REG 0x124
+#define CAR_CLKSRC_I2C2_REG 0x198
+#define CAR_CLKSRC_I2C3_REG 0x1b8
+#define CAR_CLKSRC_I2C4_REG 0x3c4
+#define CAR_CLKSRC_I2C5_REG 0x128
+#define CAR_CLKSRC_I2C6_REG 0x65c
-#define CAR_CLKSRC_I2C_SRC __BITS(31,29)
-#define CAR_CLKSRC_I2C_SRC_PLLP_OUT0 0
-#define CAR_CLKSRC_I2C_SRC_PLLC2_OUT0 1
-#define CAR_CLKSRC_I2C_SRC_PLLC_OUT0 2
-#define CAR_CLKSRC_I2C_SRC_PLLC4_OUT0 3
-#define CAR_CLKSRC_I2C_SRC_PLLC4_OUT1 5
-#define CAR_CLKSRC_I2C_SRC_CLK_M 6
-#define CAR_CLKSRC_I2C_SRC_PLLC4_OUT2 7
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