[src/trunk]: src/sys/arch/x86/x86 Improve the detection. Future generations o...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/72d7f6731e17
branches:  trunk
changeset: 831447:72d7f6731e17
user:      maxv <maxv%NetBSD.org@localhost>
date:      Fri Mar 30 19:58:05 2018 +0000

description:
Improve the detection. Future generations of Intel CPUs will have a bit to
say they are not affected by Meltdown.

diffstat:

 sys/arch/x86/x86/svs.c |  17 +++++++++++++++--
 1 files changed, 15 insertions(+), 2 deletions(-)

diffs (40 lines):

diff -r 9406d7f4f091 -r 72d7f6731e17 sys/arch/x86/x86/svs.c
--- a/sys/arch/x86/x86/svs.c    Fri Mar 30 19:51:53 2018 +0000
+++ b/sys/arch/x86/x86/svs.c    Fri Mar 30 19:58:05 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: svs.c,v 1.16 2018/03/29 07:24:26 maxv Exp $    */
+/*     $NetBSD: svs.c,v 1.17 2018/03/30 19:58:05 maxv Exp $    */
 
 /*
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: svs.c,v 1.16 2018/03/29 07:24:26 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: svs.c,v 1.17 2018/03/30 19:58:05 maxv Exp $");
 
 #include "opt_svs.h"
 
@@ -750,8 +750,21 @@
 void
 svs_init(void)
 {
+       uint64_t msr;
+
        if (cpu_vendor != CPUVENDOR_INTEL) {
                return;
        }
+       if (cpu_info_primary.ci_feat_val[7] & CPUID_SEF_ARCH_CAP) {
+               msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
+               if (msr & IA32_ARCH_RDCL_NO) {
+                       /*
+                        * The processor indicates it is not vulnerable to the
+                        * Rogue Data Cache Load (Meltdown) flaw.
+                        */
+                       return;
+               }
+       }
+
        svs_enable();
 }