[src/trunk]: src/sys/arch/arm/marvell Add support for timers on Armada XP.

[rkujawa <rkujawa%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8852aa307aa3
branches:  trunk
changeset: 786555:8852aa307aa3
user:      rkujawa <rkujawa%NetBSD.org@localhost>
date:      Wed May 01 12:45:31 2013 +0000

description:
Add support for timers on Armada XP.

Obtained from Marvell, Semihalf.

diffstat:

 sys/arch/arm/marvell/mvsoctmr.c    |  43 ++++++++++++++++++++++++++++++++++---
 sys/arch/arm/marvell/mvsoctmrreg.h |   9 ++++---
 2 files changed, 44 insertions(+), 8 deletions(-)

diffs (132 lines):

diff -r 67cc7d1373d2 -r 8852aa307aa3 sys/arch/arm/marvell/mvsoctmr.c
--- a/sys/arch/arm/marvell/mvsoctmr.c   Wed May 01 12:38:06 2013 +0000
+++ b/sys/arch/arm/marvell/mvsoctmr.c   Wed May 01 12:45:31 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mvsoctmr.c,v 1.8 2012/07/22 19:35:04 jakllsch Exp $    */
+/*     $NetBSD: mvsoctmr.c,v 1.9 2013/05/01 12:45:31 rkujawa Exp $     */
 /*
  * Copyright (c) 2007, 2008 KIYOHARA Takashi
  * All rights reserved.
@@ -25,9 +25,10 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.8 2012/07/22 19:35:04 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.9 2013/05/01 12:45:31 rkujawa Exp $");
 
 #include "opt_ddb.h"
+#include "opt_mvsoc.h"
 
 #include <sys/param.h>
 #include <sys/atomic.h>
@@ -67,6 +68,9 @@
 
        bus_space_tag_t sc_iot;
        bus_space_handle_t sc_ioh;
+#if defined(ARMADAXP)
+       int sc_irq;
+#endif
 };
 
 
@@ -133,6 +137,10 @@
        if (mvsoctmr_sc == NULL)
                mvsoctmr_sc = sc;
 
+#if defined(ARMADAXP)
+       sc->sc_irq = mva->mva_irq;
+#endif
+
        sc->sc_dev = self;
        sc->sc_iot = mva->mva_iot;
        if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
@@ -177,6 +185,12 @@
 {
        struct clockframe *frame = arg;
 
+#if defined(ARMADAXP)
+       /* Acknowledge all timers-related interrupts */
+       bus_space_write_4(mvsoctmr_sc->sc_iot, mvsoctmr_sc->sc_ioh,
+           MVSOCTMR_TESR, 0x0);
+#endif
+
        hardclock(frame);
 
        return 1;
@@ -211,16 +225,33 @@
                panic("cpu_initclocks: mvsoctmr not found");
 
        mvsoctmr_timecounter.tc_priv = sc;
-       mvsoctmr_timecounter.tc_frequency = mvTclk;
 
-       timer0_tval = (mvTclk * 2) / (u_long) hz;
+#if defined(ARMADAXP)
+       /* We set global timer and counter to 25 MHz mode */
+       mvsoctmr_timecounter.tc_frequency = 25000000;
+#else
+       mvsoctmr_timecounter.tc_frequency = mvTclk;
+#endif
+
+       timer0_tval = (mvsoctmr_timecounter.tc_frequency * 2) / (u_long) hz;
        timer0_tval = (timer0_tval / 2) + (timer0_tval & 1);
 
        mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, timer0_tval, en, autoen);
        mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, en, autoen);
 
+#if defined(ARMADAXP)
+       /*
+        * Establishing timer interrupts is slightly different for Armada XP
+        * than for other supported SoCs from Marvell.
+        * Timer interrupt is no different from any other interrupt in Armada
+        * XP, so we use generic marvell_intr_establish().
+        */
+       clock_ih = marvell_intr_establish(sc->sc_irq, IPL_CLOCK,
+           clockhandler, NULL);
+#else
        clock_ih = mvsoc_bridge_intr_establish(MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ,
            IPL_CLOCK, clockhandler, NULL);
+#endif
        if (clock_ih == NULL)
                panic("cpu_initclocks: unable to register timer interrupt");
 
@@ -303,6 +334,10 @@
                ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num);
        else
                ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num);
+#if defined(ARMADAXP)
+       /* Set timer and counter to 25MHz mode */
+       ctrl |= MVSOCTMR_CTCR_25MHZEN(num);
+#endif
        bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl);
 }
 
diff -r 67cc7d1373d2 -r 8852aa307aa3 sys/arch/arm/marvell/mvsoctmrreg.h
--- a/sys/arch/arm/marvell/mvsoctmrreg.h        Wed May 01 12:38:06 2013 +0000
+++ b/sys/arch/arm/marvell/mvsoctmrreg.h        Wed May 01 12:45:31 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mvsoctmrreg.h,v 1.1 2010/10/03 05:49:24 kiyohara Exp $ */
+/*     $NetBSD: mvsoctmrreg.h,v 1.2 2013/05/01 12:45:31 rkujawa Exp $  */
 /*
  * Copyright (c) 2007 KIYOHARA Takashi
  * All rights reserved.
@@ -30,6 +30,7 @@
 #define MVSOCTMR_SIZE          0x100
 
 #define MVSOCTMR_CTCR          0x00            /* CPU Timers Control */
+#define MVSOCTMR_TESR          0x04            /* CPU Timers Event Status */
 #define MVSOCTMR_RELOAD(n)     (0x10 + (n) * 8)/* CPU Timer(n) Reload */
 #define MVSOCTMR_TIMER(n)      (0x14 + (n) * 8)/* CPU Timer(n) */
 
@@ -37,9 +38,9 @@
 #define MVSOCTMR_TIMER1                1
 #define MVSOCTMR_WATCHDOG      2
 
-
 /* CPU Timers Control Register (MVSOCTMR_CTCR) */
-#define MVSOCTMR_CTCR_CPUTIMEREN(n)    (1 << (n * 2))
-#define MVSOCTMR_CTCR_CPUTIMERAUTO(n)  (1 << (n * 2 + 1))
+#define MVSOCTMR_CTCR_CPUTIMEREN(n)    (1 << ((n) * 2))
+#define MVSOCTMR_CTCR_CPUTIMERAUTO(n)  (1 << ((n) * 2 + 1))
+#define MVSOCTMR_CTCR_25MHZEN(n)       (1 << ((n) + 11))
 
 #endif /* !_MVSOCTMRREG_H_ */