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[src/trunk]: src/sys/arch Add support for PCI MSI using ARM GICv2m.
details: https://anonhg.NetBSD.org/src/rev/d8a7ab6e049f
branches: trunk
changeset: 836506:d8a7ab6e049f
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Oct 21 00:42:05 2018 +0000
description:
Add support for PCI MSI using ARM GICv2m.
diffstat:
sys/arch/arm/acpi/acpi_pci_machdep.c | 28 ++-
sys/arch/arm/acpi/gic_acpi.c | 60 +++++++-
sys/arch/arm/cortex/files.cortex | 3 +-
sys/arch/arm/cortex/gic_v2m.c | 218 +++++++++++++++++++++++++++++++
sys/arch/arm/cortex/gic_v2m.h | 51 +++++++
sys/arch/arm/fdt/acpi_fdt.c | 7 +-
sys/arch/arm/include/pci_machdep.h | 64 +++++++++-
sys/arch/arm/pci/files.pci | 4 +
sys/arch/arm/pci/pci_msi_machdep.c | 241 +++++++++++++++++++++++++++++++++++
sys/arch/arm/pci/pci_msi_machdep.h | 57 ++++++++
sys/arch/evbarm/conf/files.evbarm | 6 +-
sys/arch/evbarm/conf/std.generic64 | 3 +-
12 files changed, 721 insertions(+), 21 deletions(-)
diffs (truncated from 949 to 300 lines):
diff -r cbd66f10dce6 -r d8a7ab6e049f sys/arch/arm/acpi/acpi_pci_machdep.c
--- a/sys/arch/arm/acpi/acpi_pci_machdep.c Sun Oct 21 00:26:24 2018 +0000
+++ b/sys/arch/arm/acpi/acpi_pci_machdep.c Sun Oct 21 00:42:05 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: acpi_pci_machdep.c,v 1.2 2018/10/19 11:40:27 jmcneill Exp $ */
+/* $NetBSD: acpi_pci_machdep.c,v 1.3 2018/10/21 00:42:05 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: acpi_pci_machdep.c,v 1.2 2018/10/19 11:40:27 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: acpi_pci_machdep.c,v 1.3 2018/10/21 00:42:05 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -57,8 +57,7 @@
#include <arm/acpi/acpi_pci_machdep.h>
-#define IH_INDEX_MASK 0x0000ffff
-#define IH_MPSAFE 0x80000000
+#include <arm/pci/pci_msi_machdep.h>
struct acpi_pci_prt {
u_int prt_bus;
@@ -331,7 +330,13 @@
static const char *
acpi_pci_md_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
{
- snprintf(buf, len, "irq %d", (int)(ih & IH_INDEX_MASK));
+ const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);
+
+ if (ih & ARM_PCI_INTR_MSI)
+ snprintf(buf, len, "irq %d (MSI)", irq);
+ else
+ snprintf(buf, len, "irq %d", irq);
+
return buf;
}
@@ -347,9 +352,9 @@
switch (attr) {
case PCI_INTR_MPSAFE:
if (data)
- *ih |= IH_MPSAFE;
+ *ih |= ARM_PCI_INTR_MPSAFE;
else
- *ih &= ~IH_MPSAFE;
+ *ih &= ~ARM_PCI_INTR_MPSAFE;
return 0;
default:
return ENODEV;
@@ -360,8 +365,13 @@
acpi_pci_md_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
int (*callback)(void *), void *arg)
{
- const int irq = ih & IH_INDEX_MASK;
- const int mpsafe = (ih & IH_MPSAFE) ? IST_MPSAFE : 0;
+ struct acpi_pci_context * const ap = v;
+
+ if (ih & ARM_PCI_INTR_MSI)
+ return arm_pci_msi_intr_establish(&ap->ap_pc, ih, ipl, callback, arg);
+
+ const int irq = (int)__SHIFTOUT(ih, ARM_PCI_INTR_IRQ);
+ const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? IST_MPSAFE : 0;
return intr_establish(irq, ipl, IST_LEVEL | mpsafe, callback, arg);
}
diff -r cbd66f10dce6 -r d8a7ab6e049f sys/arch/arm/acpi/gic_acpi.c
--- a/sys/arch/arm/acpi/gic_acpi.c Sun Oct 21 00:26:24 2018 +0000
+++ b/sys/arch/arm/acpi/gic_acpi.c Sun Oct 21 00:42:05 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_acpi.c,v 1.1 2018/10/12 22:20:04 jmcneill Exp $ */
+/* $NetBSD: gic_acpi.c,v 1.2 2018/10/21 00:42:05 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,30 +30,36 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic_acpi.c,v 1.1 2018/10/12 22:20:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_acpi.c,v 1.2 2018/10/21 00:42:05 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/device.h>
+#include <sys/kmem.h>
#include <dev/acpi/acpireg.h>
#include <dev/acpi/acpivar.h>
#include <arm/cortex/gic_intr.h>
+#include <arm/cortex/gic_reg.h>
+#include <arm/cortex/gic_v2m.h>
#include <arm/cortex/mpcore_var.h>
#include <dev/fdt/fdtvar.h>
-#define GICD_SIZE 0x1000
-#define GICC_SIZE 0x1000
+#define GICD_SIZE 0x1000
+#define GICC_SIZE 0x1000
+#define GICMSIFRAME_SIZE 0x1000
extern struct bus_space arm_generic_bs_tag;
+extern struct pic_softc *pic_list[];
static int gic_acpi_match(device_t, cfdata_t, void *);
static void gic_acpi_attach(device_t, device_t, void *);
static ACPI_STATUS gic_acpi_find_gicc(ACPI_SUBTABLE_HEADER *, void *);
+static ACPI_STATUS gic_acpi_find_msi_frame(ACPI_SUBTABLE_HEADER *, void *);
CFATTACH_DECL_NEW(gic_acpi, 0, gic_acpi_match, gic_acpi_attach, NULL, NULL);
@@ -85,6 +91,7 @@
ACPI_MADT_GENERIC_DISTRIBUTOR *gicd = aux;
ACPI_MADT_GENERIC_INTERRUPT *gicc = NULL;
bus_space_handle_t bsh;
+ device_t armgic;
int error;
acpi_madt_walk(gic_acpi_find_gicc, &gicc);
@@ -114,9 +121,11 @@
.mpcaa_off2 = gicc->BaseAddress - addr,
};
- config_found(self, &mpcaa, NULL);
+ armgic = config_found(self, &mpcaa, NULL);
arm_fdt_irq_set_handler(armgic_irq_handler);
+
+ acpi_madt_walk(gic_acpi_find_msi_frame, armgic);
}
static ACPI_STATUS
@@ -131,3 +140,44 @@
return AE_LIMIT;
}
+
+static ACPI_STATUS
+gic_acpi_find_msi_frame(ACPI_SUBTABLE_HEADER *hdrp, void *aux)
+{
+ ACPI_MADT_GENERIC_MSI_FRAME *msi_frame = (ACPI_MADT_GENERIC_MSI_FRAME *)hdrp;
+ struct gic_v2m_frame *frame;
+ struct pic_softc *pic = pic_list[0];
+ device_t armgic = aux;
+
+ if (hdrp->Type != ACPI_MADT_TYPE_GENERIC_MSI_FRAME)
+ return AE_OK;
+
+ frame = kmem_zalloc(sizeof(*frame), KM_SLEEP);
+ frame->frame_reg = msi_frame->BaseAddress;
+ frame->frame_pic = pic;
+ if (msi_frame->Flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
+ frame->frame_base = msi_frame->SpiBase;
+ frame->frame_count = msi_frame->SpiCount;
+ } else {
+ bus_space_tag_t bst = &arm_generic_bs_tag;
+ bus_space_handle_t bsh;
+ if (bus_space_map(bst, frame->frame_reg, GICMSIFRAME_SIZE, 0, &bsh) != 0) {
+ printf("%s: failed to map frame\n", __func__);
+ return AE_OK;
+ }
+ const uint32_t typer = bus_space_read_4(bst, bsh, GIC_MSI_TYPER);
+ bus_space_unmap(bst, bsh, GICMSIFRAME_SIZE);
+
+ frame->frame_base = __SHIFTOUT(typer, GIC_MSI_TYPER_BASE);
+ frame->frame_count = __SHIFTOUT(typer, GIC_MSI_TYPER_NUMBER);
+ }
+
+ if (gic_v2m_init(frame, armgic, msi_frame->MsiFrameId) != 0)
+ aprint_error_dev(armgic, "failed to initialize GICv2m\n");
+ else
+ aprint_normal_dev(armgic, "GICv2m @ %#" PRIx64 ", SPIs %u-%u\n",
+ (uint64_t)frame->frame_reg, frame->frame_base,
+ frame->frame_base + frame->frame_count);
+
+ return AE_OK;
+}
diff -r cbd66f10dce6 -r d8a7ab6e049f sys/arch/arm/cortex/files.cortex
--- a/sys/arch/arm/cortex/files.cortex Sun Oct 21 00:26:24 2018 +0000
+++ b/sys/arch/arm/cortex/files.cortex Sun Oct 21 00:42:05 2018 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.8 2018/08/08 19:02:28 jmcneill Exp $
+# $NetBSD: files.cortex,v 1.9 2018/10/21 00:42:05 jmcneill Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -15,6 +15,7 @@
device armgic: pic, pic_splfuncs
attach armgic at mpcorebus
file arch/arm/cortex/gic.c armgic
+file arch/arm/cortex/gic_v2m.c armgic & pci & __have_pci_msi_msix
# ARM Generic Interrupt Controller v3+
device gicvthree: pic, pic_splfuncs
diff -r cbd66f10dce6 -r d8a7ab6e049f sys/arch/arm/cortex/gic_v2m.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/cortex/gic_v2m.c Sun Oct 21 00:42:05 2018 +0000
@@ -0,0 +1,218 @@
+/* $NetBSD: gic_v2m.c,v 1.1 2018/10/21 00:42:05 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jared McNeill <jmcneill%invisible.ca@localhost>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define _INTR_PRIVATE
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.1 2018/10/21 00:42:05 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/kmem.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <arm/pic/picvar.h>
+#include <arm/cortex/gic_v2m.h>
+
+static int
+gic_v2m_msi_alloc_spi(struct gic_v2m_frame *frame, int count,
+ const struct pci_attach_args *pa)
+{
+ int spi, n;
+
+ for (spi = frame->frame_base;
+ spi < frame->frame_base + frame->frame_count; ) {
+ if (frame->frame_pa[spi] == NULL) {
+ for (n = 1; n < count; n++)
+ if (frame->frame_pa[spi + n] != NULL)
+ goto next_spi;
+
+ for (n = 0; n < count; n++)
+ frame->frame_pa[spi + n] = pa;
+
+ return spi;
+ }
+next_spi:
+ spi += count;
+ }
+
+ return -1;
+}
+
+static void
+gic_v2m_msi_free_spi(struct gic_v2m_frame *frame, int spi)
+{
+ frame->frame_pa[spi] = NULL;
+}
+
+static int
+gic_v2m_msi_available_spi(struct gic_v2m_frame *frame)
+{
+ int spi, n;
+
+ for (spi = frame->frame_base, n = 0;
+ spi < frame->frame_base + frame->frame_count;
+ spi++) {
+ if (frame->frame_pa[spi] == NULL)
+ n++;
+ }
+
+ return n;
+}
+
+static void
+gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi)
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