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[src/trunk]: src/sys/arch/arm/nvidia More XUSB init. A USB3 memory stick seem...
details: https://anonhg.NetBSD.org/src/rev/e0a9df838b1c
branches: trunk
changeset: 826722:e0a9df838b1c
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Sep 24 20:09:53 2017 +0000
description:
More XUSB init. A USB3 memory stick seems to work now.
diffstat:
sys/arch/arm/nvidia/tegra210_car.c | 58 +++++-
sys/arch/arm/nvidia/tegra210_carreg.h | 15 +-
sys/arch/arm/nvidia/tegra210_xusbpad.c | 366 ++++++++++++++++++--------------
sys/arch/arm/nvidia/tegra_var.h | 5 +-
4 files changed, 282 insertions(+), 162 deletions(-)
diffs (truncated from 616 to 300 lines):
diff -r 1bc4b0c8b810 -r e0a9df838b1c sys/arch/arm/nvidia/tegra210_car.c
--- a/sys/arch/arm/nvidia/tegra210_car.c Sun Sep 24 20:09:22 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_car.c Sun Sep 24 20:09:53 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_car.c,v 1.9 2017/09/23 23:58:31 jmcneill Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.10 2017/09/24 20:09:53 jmcneill Exp $ */
/*-
* Copyright (c) 2015-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.9 2017/09/23 23:58:31 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.10 2017/09/24 20:09:53 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -559,6 +559,8 @@
CLK_GATE_Y("USB2_TRK", "UBS2_HSIC_TRK", CAR_DEV_Y_USB2_TRK),
CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK),
CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA),
+ CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD),
+ CLK_GATE_H("USB2", "PLL_U_480M", CAR_DEV_H_USB2),
};
struct tegra210_init_parent {
@@ -761,6 +763,8 @@
tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
0x3, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT);
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_USBD);
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_USB2);
bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_XUSB);
bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_PEX_USB_UPHY);
bus_space_write_4(bst, bsh, CAR_RST_DEV_Y_CLR_REG, CAR_DEV_Y_SATA_USB_UPHY);
@@ -827,6 +831,24 @@
delay(2);
/*
+ * Now switch PLLU to hw controlled mode.
+ */
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE);
+ tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG,
+ CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
+ CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
+ CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET,
+ CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
+ CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
+ tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0,
+ CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY);
+ delay(1);
+ tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG,
+ CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE, 0);
+ delay(1);
+ tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB);
+
+ /*
* Set up PLLREFE
*/
tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG,
@@ -1510,3 +1532,35 @@
return 0;
}
+
+void
+tegra210_car_xusbio_enable_hw_control(void)
+{
+ device_t dev = device_find_by_driver_unit("tegra210car", 0);
+ KASSERT(dev != NULL);
+ struct tegra210_car_softc * const sc = device_private(dev);
+ bus_space_tag_t bst = sc->sc_bst;
+ bus_space_handle_t bsh = sc->sc_bsh;
+
+ tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG,
+ 0,
+ CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
+ CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
+ tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG,
+ CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ |
+ CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET,
+ 0);
+}
+
+void
+tegra210_car_xusbio_enable_hw_seq(void)
+{
+ device_t dev = device_find_by_driver_unit("tegra210car", 0);
+ KASSERT(dev != NULL);
+ struct tegra210_car_softc * const sc = device_private(dev);
+ bus_space_tag_t bst = sc->sc_bst;
+ bus_space_handle_t bsh = sc->sc_bsh;
+
+ tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG,
+ CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0);
+}
diff -r 1bc4b0c8b810 -r e0a9df838b1c sys/arch/arm/nvidia/tegra210_carreg.h
--- a/sys/arch/arm/nvidia/tegra210_carreg.h Sun Sep 24 20:09:22 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_carreg.h Sun Sep 24 20:09:53 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_carreg.h,v 1.6 2017/09/23 23:21:35 jmcneill Exp $ */
+/* $NetBSD: tegra210_carreg.h,v 1.7 2017/09/24 20:09:53 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -614,6 +614,19 @@
#define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE __BIT(1)
#define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL __BIT(0)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG 0x530
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE __BIT(28)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_STATE __BITS(27,26)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_START_STATE __BIT(25)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE __BIT(24)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT __BIT(7)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET __BIT(6)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_IN_SWCTL __BIT(4)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_OVERRIDE_VALUE __BIT(3)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL __BIT(2)
+#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL __BIT(0)
+
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG 0x534
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_CLK_SWITCH_DLY __BITS(31,24)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY __BITS(23,14)
diff -r 1bc4b0c8b810 -r e0a9df838b1c sys/arch/arm/nvidia/tegra210_xusbpad.c
--- a/sys/arch/arm/nvidia/tegra210_xusbpad.c Sun Sep 24 20:09:22 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_xusbpad.c Sun Sep 24 20:09:53 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_xusbpad.c,v 1.5 2017/09/23 23:21:35 jmcneill Exp $ */
+/* $NetBSD: tegra210_xusbpad.c,v 1.6 2017/09/24 20:09:53 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.5 2017/09/23 23:21:35 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.6 2017/09/24 20:09:53 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -62,6 +62,10 @@
#define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN_EARLY(n) __BIT((n) * 3 + 1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN(n) __BIT((n) * 3 + 0)
+#define XUSB_PADCTL_USB3_PAD_MUX_REG 0x28
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE __BIT(8)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE(n) __BIT(1 + (n))
+
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV __BITS(29,28)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV __BITS(27,20)
@@ -130,39 +134,201 @@
static const char * tegra210_xusbpad_hsic_func[] = { "snps", "xusb" };
static const char * tegra210_xusbpad_pcie_func[] = { "pcie-x1", "usb3-ss", "sata", "pcie-x4" };
-#define XUSBPAD_LANE(n, r, m, f) \
+static void
+tegra210_xusbpad_uphy_enable_pcie(struct tegra210_xusbpad_softc *sc)
+{
+ uint32_t val;
+ int retry;
+
+ /* UPHY PLLs */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,
+ __SHIFTIN(0x136, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL),
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_5_REG,
+ __SHIFTIN(0x2a, XUSB_PADCTL_UPHY_PLL_P0_CTL_5_DCO_CTRL),
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_5_DCO_CTRL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_1_PWR_OVRD, 0);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_OVRD, 0);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_OVRD, 0);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLK_SEL),
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLK_SEL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG,
+ __SHIFTIN(2, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL),
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_EN, 0);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV),
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,
+ __SHIFTIN(0x19, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV),
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV),
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_IDDQ);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_SLEEP);
+
+ delay(20);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLKBUF_EN, 0);
+
+ /* Calibration */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_EN, 0);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_DONE) != 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (1)\n");
+ return;
+ }
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_EN);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_DONE) == 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (2)\n");
+ return;
+ }
+
+ /* Enable the PLL */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_1_ENABLE, 0);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_1_LOCKDET_STATUS) != 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout enabling UPHY PLL\n");
+ return;
+ }
+
+ /* RCAL */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_EN, 0);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,
+ XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_CLK_EN, 0);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_DONE) != 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (3)\n");
+ return;
+ }
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_EN);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_DONE) == 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (4)\n");
+ return;
+ }
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_CLK_EN);
+
+ tegra210_car_xusbio_enable_hw_control();
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_PWR_OVRD);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_OVRD);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_OVRD);
+
+ delay(1);
+
+ tegra210_car_xusbio_enable_hw_seq();
+}
+
+static void
+tegra210_xusbpad_lane_enable_pcie(struct tegra210_xusbpad_softc *sc, int index)
+{
+ tegra210_xusbpad_uphy_enable_pcie(sc);
+
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