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[src/trunk]: src/sys/arch/arm/nvidia USB works on Tegra X1 now.
details: https://anonhg.NetBSD.org/src/rev/e579de79ea1c
branches: trunk
changeset: 826725:e579de79ea1c
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Mon Sep 25 00:03:34 2017 +0000
description:
USB works on Tegra X1 now.
diffstat:
sys/arch/arm/nvidia/tegra210_car.c | 78 +++++++++++++++++------
sys/arch/arm/nvidia/tegra210_xusbpad.c | 105 +++++++++++++++++++++++++++++---
sys/arch/arm/nvidia/tegra_xusb.c | 68 +++++++++++++-------
3 files changed, 194 insertions(+), 57 deletions(-)
diffs (truncated from 439 to 300 lines):
diff -r b48379600288 -r e579de79ea1c sys/arch/arm/nvidia/tegra210_car.c
--- a/sys/arch/arm/nvidia/tegra210_car.c Mon Sep 25 00:03:10 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_car.c Mon Sep 25 00:03:34 2017 +0000
@@ -1,4 +1,5 @@
-/* $NetBSD: tegra210_car.c,v 1.10 2017/09/24 20:09:53 jmcneill Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $ */
+#define TEGRA210_CAR_DEBUG
/*-
* Copyright (c) 2015-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.10 2017/09/24 20:09:53 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -538,6 +539,15 @@
CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV),
CLK_DIV("USB2_HSIC_TRK", "CLK_M",
CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV),
+ CLK_DIV("DIV_PLL_U_OUT1", "PLL_U",
+ CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RATIO),
+ CLK_DIV("DIV_PLL_U_OUT2", "PLL_U",
+ CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RATIO),
+
+ CLK_GATE("PLL_U_OUT1", "DIV_PLL_U_OUT1",
+ CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN),
+ CLK_GATE("PLL_U_OUT2", "DIV_PLL_U_OUT2",
+ CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_CLKEN),
CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA),
CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB),
@@ -553,10 +563,11 @@
CLK_GATE_V("I2C4", "DIV_I2C4", CAR_DEV_V_I2C4),
CLK_GATE_H("I2C5", "DIV_I2C5", CAR_DEV_H_I2C5),
CLK_GATE_X("I2C6", "DIV_I2C6", CAR_DEV_X_I2C6),
+ CLK_GATE_W("XUSB_GATE", "CLK_M", CAR_DEV_W_XUSB),
CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST),
CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS),
CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE),
- CLK_GATE_Y("USB2_TRK", "UBS2_HSIC_TRK", CAR_DEV_Y_USB2_TRK),
+ CLK_GATE_Y("USB2_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_USB2_TRK),
CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK),
CLK_GATE_H("APBDMA", "CLK_M", CAR_DEV_H_APBDMA),
CLK_GATE_L("USBD", "PLL_U_480M", CAR_DEV_L_USBD),
@@ -566,15 +577,20 @@
struct tegra210_init_parent {
const char *clock;
const char *parent;
+ u_int rate;
+ u_int enable;
} tegra210_init_parents[] = {
- { "SDMMC1", "PLL_P" },
- { "SDMMC2", "PLL_P" },
- { "SDMMC3", "PLL_P" },
- { "SDMMC4", "PLL_P" },
- { "XUSB_HOST_SRC", "PLL_P" },
- { "XUSB_FALCON_SRC", "PLL_P" },
- { "XUSB_SS_SRC", "PLL_U_480M" },
- { "XUSB_FS_SRC", "PLL_U_48M" },
+ { "SDMMC1", "PLL_P", 0, 0 },
+ { "SDMMC2", "PLL_P", 0, 0 },
+ { "SDMMC3", "PLL_P", 0, 0 },
+ { "SDMMC4", "PLL_P", 0, 0 },
+ { "XUSB_GATE", NULL, 0, 1 },
+ { "XUSB_HOST_SRC", "PLL_P", 102000000, 0 },
+ { "XUSB_FALCON_SRC", "PLL_P", 204000000, 0 },
+ { "XUSB_SS_SRC", "PLL_U_480M", 120000000, 0 },
+ { "XUSB_FS_SRC", "PLL_U_48M", 48000000, 0 },
+ { "PLL_U_OUT1", NULL, 48000000, 1 },
+ { "PLL_U_OUT2", NULL, 60000000, 1 },
};
struct tegra210_car_rst {
@@ -719,18 +735,38 @@
for (n = 0; n < __arraycount(tegra210_init_parents); n++) {
clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock);
- KASSERT(clk != NULL);
- clk_parent = clk_get(&sc->sc_clkdom,
- tegra210_init_parents[n].parent);
- KASSERT(clk_parent != NULL);
+ KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock);
+
+ if (tegra210_init_parents[n].parent != NULL) {
+ clk_parent = clk_get(&sc->sc_clkdom,
+ tegra210_init_parents[n].parent);
+ KASSERT(clk_parent != NULL);
- error = clk_set_parent(clk, clk_parent);
- if (error) {
- aprint_error_dev(sc->sc_dev,
- "couldn't set '%s' parent to '%s': %d\n",
- clk->name, clk_parent->name, error);
+ error = clk_set_parent(clk, clk_parent);
+ if (error) {
+ aprint_error_dev(sc->sc_dev,
+ "couldn't set '%s' parent to '%s': %d\n",
+ clk->name, clk_parent->name, error);
+ }
+ clk_put(clk_parent);
}
- clk_put(clk_parent);
+ if (tegra210_init_parents[n].rate != 0) {
+ error = clk_set_rate(clk, tegra210_init_parents[n].rate);
+ if (error) {
+ aprint_error_dev(sc->sc_dev,
+ "couldn't set '%s' rate to %u Hz: %d\n",
+ clk->name, tegra210_init_parents[n].rate,
+ error);
+ }
+ }
+ if (tegra210_init_parents[n].enable) {
+ error = clk_enable(clk);
+ if (error) {
+ aprint_error_dev(sc->sc_dev,
+ "couldn't enable '%s': %d\n", clk->name,
+ error);
+ }
+ }
clk_put(clk);
}
}
diff -r b48379600288 -r e579de79ea1c sys/arch/arm/nvidia/tegra210_xusbpad.c
--- a/sys/arch/arm/nvidia/tegra210_xusbpad.c Mon Sep 25 00:03:10 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_xusbpad.c Mon Sep 25 00:03:34 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_xusbpad.c,v 1.6 2017/09/24 20:09:53 jmcneill Exp $ */
+/* $NetBSD: tegra210_xusbpad.c,v 1.7 2017/09/25 00:03:34 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.6 2017/09/24 20:09:53 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.7 2017/09/25 00:03:34 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -66,6 +66,33 @@
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE __BIT(8)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE(n) __BIT(1 + (n))
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_REG(n) (0x84 + (n) * 0x40)
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_VREG_LEV __BITS(8,7)
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_VREG_FIX18 __BIT(6)
+
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_REG(n) (0x88 + (n) * 0x40)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD_ZI __BIT(29)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD2 __BIT(27)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD __BIT(26)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_HS_CURR_LEVEL __BITS(5,0)
+
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_REG(n) (0x8c + (n) * 0x40)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_RPD_CTRL __BITS(30,26)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_TERM_RANGE_ADJ __BITS(6,3)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_DR __BIT(2)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_DISC_OVRD __BIT(1)
+#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_CHRP_OVRD __BIT(0)
+
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_REG 0x284
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_PD __BIT(11)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_DISCON_LEVEL __BITS(5,3)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_SQUELCH_LEVEL __BITS(2,0)
+
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_REG 0x288
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_PD_TRK __BIT(26)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_DONE_RESET_TIMER __BITS(25,19)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_START_TIMER __BITS(18,12)
+
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV __BITS(29,28)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV __BITS(27,20)
@@ -112,6 +139,14 @@
#define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_6_REG(n) (0xa74 + (n) * 0x40)
+#define FUSE_SKUCALIB_REG 0xf0
+#define FUSE_SKUCALIB_HS_CURR_LEVEL(n) \
+ ((n) == 0 ? __BITS(6,0) : __BITS(((n) - 1) * 6 + 17, ((n) - 1) * 6 + 11))
+#define FUSE_SKUCALIB_HS_TERM_RANGE_ADJ __BITS(10,7)
+
+#define FUSE_USBCALIB_REG 0x250
+#define FUSE_USBCALIB_EXT_RPD_CTRL __BITS(4,0)
+
struct tegra210_xusbpad_softc {
device_t sc_dev;
int sc_phandle;
@@ -278,6 +313,59 @@
XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE(index), 0);
}
+static void
+tegra210_xusbpad_lane_enable_usb2(struct tegra210_xusbpad_softc *sc, int index)
+{
+ uint32_t skucalib, usbcalib;
+
+ skucalib = tegra_fuse_read(FUSE_SKUCALIB_REG);
+ const u_int hs_curr_level = __SHIFTOUT(skucalib, FUSE_SKUCALIB_HS_CURR_LEVEL((u_int)index));
+ const u_int hs_term_range_adj = __SHIFTOUT(skucalib, FUSE_SKUCALIB_HS_TERM_RANGE_ADJ);
+
+ usbcalib = tegra_fuse_read(FUSE_USBCALIB_REG);
+ const u_int ext_rpd_ctrl = __SHIFTOUT(usbcalib, FUSE_USBCALIB_EXT_RPD_CTRL);
+
+ SETCLR4(sc, XUSB_PADCTL_USB2_PAD_MUX_REG,
+ __SHIFTIN(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB,
+ XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD),
+ XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD);
+
+ SETCLR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_REG,
+ __SHIFTIN(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_DISCON_LEVEL) |
+ __SHIFTIN(0x0, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_SQUELCH_LEVEL),
+ XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_DISCON_LEVEL |
+ XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_SQUELCH_LEVEL);
+ SETCLR4(sc, XUSB_PADCTL_USB2_OTG_PADn_CTL_0_REG(index),
+ __SHIFTIN(hs_curr_level, XUSB_PADCTL_USB2_OTG_PADn_CTL_0_HS_CURR_LEVEL),
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_0_HS_CURR_LEVEL |
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD |
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD2 |
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD_ZI);
+ SETCLR4(sc, XUSB_PADCTL_USB2_OTG_PADn_CTL_1_REG(index),
+ __SHIFTIN(hs_term_range_adj, XUSB_PADCTL_USB2_OTG_PADn_CTL_1_TERM_RANGE_ADJ) |
+ __SHIFTIN(ext_rpd_ctrl, XUSB_PADCTL_USB2_OTG_PADn_CTL_1_RPD_CTRL),
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_1_TERM_RANGE_ADJ |
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_1_RPD_CTRL |
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_DR |
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_CHRP_OVRD |
+ XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_DISC_OVRD);
+ SETCLR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_REG(index),
+ XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_VREG_FIX18,
+ XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_VREG_LEV);
+
+ SETCLR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_REG,
+ __SHIFTIN(0x1e, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_START_TIMER) |
+ __SHIFTIN(0xa, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_DONE_RESET_TIMER),
+ XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_START_TIMER |
+ XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_DONE_RESET_TIMER);
+ SETCLR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_REG,
+ 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_PD);
+ delay(1);
+ SETCLR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_REG,
+ 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_PD_TRK);
+ delay(50);
+}
+
#define XUSBPAD_LANE(n, i, r, m, f, ef) \
{ \
.name = (n), \
@@ -299,13 +387,13 @@
void (*enable)(struct tegra210_xusbpad_softc *, int);
} tegra210_xusbpad_lanes[] = {
XUSBPAD_LANE("usb2-0", 0, 0x04, __BITS(1,0), tegra210_xusbpad_usb2_func,
- NULL),
+ tegra210_xusbpad_lane_enable_usb2),
XUSBPAD_LANE("usb2-1", 1, 0x04, __BITS(3,2), tegra210_xusbpad_usb2_func,
- NULL),
+ tegra210_xusbpad_lane_enable_usb2),
XUSBPAD_LANE("usb2-2", 2, 0x04, __BITS(5,4), tegra210_xusbpad_usb2_func,
- NULL),
+ tegra210_xusbpad_lane_enable_usb2),
XUSBPAD_LANE("usb2-3", 3, 0x04, __BITS(7,6), tegra210_xusbpad_usb2_func,
- NULL),
+ tegra210_xusbpad_lane_enable_usb2),
XUSBPAD_LANE("hsic-0", 0, 0x04, __BIT(14), tegra210_xusbpad_hsic_func,
NULL),
@@ -662,11 +750,6 @@
{
struct tegra210_xusbpad_softc * const sc = device_private(dev);
- SETCLR4(sc, XUSB_PADCTL_USB2_PAD_MUX_REG,
- __SHIFTIN(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB,
- XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD),
- XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD);
-
tegra210_xusbpad_enable(sc);
}
diff -r b48379600288 -r e579de79ea1c sys/arch/arm/nvidia/tegra_xusb.c
--- a/sys/arch/arm/nvidia/tegra_xusb.c Mon Sep 25 00:03:10 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra_xusb.c Mon Sep 25 00:03:34 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_xusb.c,v 1.10 2017/09/24 20:09:22 jmcneill Exp $ */
+/* $NetBSD: tegra_xusb.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $ */
/*
* Copyright (c) 2016 Jonathan A. Kollasch
@@ -30,7 +30,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.10 2017/09/24 20:09:22 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $");
#include <sys/param.h>
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