[src/trunk]: src/sys/arch/arm/nvidia Add some SMMU registers and bit definiti...

[jakllsch <jakllsch%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e6c69eaa4299
branches:  trunk
changeset: 821056:e6c69eaa4299
user:      jakllsch <jakllsch%NetBSD.org@localhost>
date:      Sun Jan 22 17:43:23 2017 +0000

description:
Add some SMMU registers and bit definitions.

diffstat:

 sys/arch/arm/nvidia/tegra_mcreg.h |  10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletions(-)

diffs (22 lines):

diff -r 5aa5edab8b3f -r e6c69eaa4299 sys/arch/arm/nvidia/tegra_mcreg.h
--- a/sys/arch/arm/nvidia/tegra_mcreg.h Sun Jan 22 17:40:06 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra_mcreg.h Sun Jan 22 17:43:23 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_mcreg.h,v 1.2 2015/11/21 16:48:33 jakllsch Exp $ */
+/* $NetBSD: tegra_mcreg.h,v 1.3 2017/01/22 17:43:23 jakllsch Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -78,4 +78,12 @@
 #define MC_EMEM_CFG_0_EMEM_BOM         __BIT(31)
 #define MC_EMEM_CFG_0_EMEM_SIZE_MB     __BITS(13,0)
 
+#define MC_SMMU_TRANSLATION_ENABLE_0_REG       0x228
+#define MC_SMMU_AFIR_ENABLE    __BIT(14)
+#define MC_SMMU_TRANSLATION_ENABLE_1_REG       0x22c
+#define MC_SMMU_AFIW_ENABLE    __BIT(17)
+#define MC_SMMU_TRANSLATION_ENABLE_2_REG       0x230
+#define MC_SMMU_TRANSLATION_ENABLE_3_REG       0x234
+#define MC_SMMU_AFI_ASID_REG   0x238
+
 #endif /* _ARM_TEGRA_MCREG_H */