[src/trunk]: src/sys/arch/aarch64/aarch64 use lr for current x30. some commen...

[nisimura <nisimura%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b900055c5cce
branches:  trunk
changeset: 826237:b900055c5cce
user:      nisimura <nisimura%NetBSD.org@localhost>
date:      Tue Aug 22 18:35:09 2017 +0000

description:
use lr for current x30. some comment snip

diffstat:

 sys/arch/aarch64/aarch64/vectors.S |  28 ++++++++++++++--------------
 1 files changed, 14 insertions(+), 14 deletions(-)

diffs (101 lines):

diff -r f3896bd4910f -r b900055c5cce sys/arch/aarch64/aarch64/vectors.S
--- a/sys/arch/aarch64/aarch64/vectors.S        Tue Aug 22 17:08:03 2017 +0000
+++ b/sys/arch/aarch64/aarch64/vectors.S        Tue Aug 22 18:35:09 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vectors.S,v 1.2 2017/08/22 17:08:03 nisimura Exp $ */
+/* $NetBSD: vectors.S,v 1.3 2017/08/22 18:35:09 nisimura Exp $ */
 
 #include <aarch64/asm.h>
 #include "assym.h"
@@ -96,7 +96,7 @@
        .p2align 11
 ENTRY(el1_vectors)
 /*
- * Exception taken from current Exception Level with SP_EL1.
+ * A64 exception taken from current Exception Level with SP_EL1.
  * (These shouldn't happen)
  */
        VECT_INVAL      1, BAD_SYNC             /* Synchronous EL1t */
@@ -104,24 +104,24 @@
        VECT_INVAL      1, BAD_FIQ              /* FIQ EL1t */
        VECT_INVAL      1, BAD_ERROR            /* Error EL1t */
 /*
- * Exception taken from current Exception Level with SP.
- * There are entries for exceptions caused in EL1 (kernel exceptions).
+ * A64 exception taken from current Exception Level with SP.
+ * EL1 (kernel exceptions)
  */
        VECT_ENTRY      el1_sync                /* Synchronous EL1h */
        VECT_ENTRY      el1_irq                 /* IRQ EL1h */
        VECT_INVAL      1, BAD_FIQ              /* FIQ EL1h */
        VECT_INVAL      1, BAD_ERROR            /* Error EL1h */
 /*
- * Exception taken from lower Exception Level which is using AArch64
- * There are entries for exceptions caused in EL0 (native user exceptions).
+ * A64 exception taken from lower Exception Level.
+ * EL0 (native user exceptions)
  */
        VECT_ENTRY      el0_sync                /* Synchronous 64bit EL0 */
        VECT_ENTRY      el0_irq                 /* IRQ 64bit EL0 */
        VECT_INVAL      0, BAD_FIQ              /* FIQ 64bit EL0 */
        VECT_INVAL      0, BAD_ERROR            /* Error 64bit EL0 */
 /*
- * Exception taken from lower Exception Level which is using AArch32
- * There are entries for exceptions caused in EL0 (compat user exceptions).
+ * A32 exception taken from lower Exception Level.
+ * EL0 (compat user exceptions)
  */
        VECT_ENTRY      el0_32sync              /* Synchronous 32bit EL0 */
        VECT_ENTRY      el0_32irq               /* IRQ 32bit EL0 */
@@ -130,7 +130,7 @@
 
 ENTRY(el1_sync)
        exception_entry 1
-       adr     x30, exception_trap_exit
+       adr     lr, exception_trap_exit
        mov     x0, sp
        mov     x1, xzr
        b       trap
@@ -138,14 +138,14 @@
 
 ENTRY(el1_irq)
        exception_entry 1
-       adr     x30, exception_trap_exit
+       adr     lr, exception_trap_exit
        mov     x0, sp
        b       interrupt
 END(el1_irq)
 
 ENTRY(el0_sync)
        exception_entry 0
-       adr     x30, exception_trap_exit
+       adr     lr, exception_trap_exit
        mov     x0, sp
        mov     x1, xzr
        b       trap
@@ -153,14 +153,14 @@
 
 ENTRY(el0_irq)
        exception_entry 0
-       adr     x30, exception_trap_exit
+       adr     lr, exception_trap_exit
        mov     x0, sp
        b       interrupt
 END(el0_irq)
 
 ENTRY(el0_32sync)
        exception_entry 0, 32
-       adr     x30, exception_trap_exit
+       adr     lr, exception_trap_exit
        mov     x0, sp
        mov     x1, xzr
        b       trap
@@ -168,7 +168,7 @@
 
 ENTRY(el0_32irq)
        exception_entry 0, 32
-       adr     x30, exception_trap_exit
+       adr     lr, exception_trap_exit
        mov     x0, sp
        b       interrupt
 END(el0_32irq)