[src/trunk]: src/sys/dev/ic Add more bits and comments, parts from jmcneill.

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ba8e36dad48c
branches:  trunk
changeset: 803242:ba8e36dad48c
user:      martin <martin%NetBSD.org@localhost>
date:      Sun Oct 19 09:39:33 2014 +0000

description:
Add more bits and comments, parts from jmcneill.

diffstat:

 sys/dev/ic/dwc_gmac_reg.h |  57 +++++++++++++++++++++++++++++-----------------
 1 files changed, 36 insertions(+), 21 deletions(-)

diffs (108 lines):

diff -r edd4021fcccf -r ba8e36dad48c sys/dev/ic/dwc_gmac_reg.h
--- a/sys/dev/ic/dwc_gmac_reg.h Sat Oct 18 16:56:51 2014 +0000
+++ b/sys/dev/ic/dwc_gmac_reg.h Sun Oct 19 09:39:33 2014 +0000
@@ -45,10 +45,16 @@
 #define        AWIN_GMAC_MAC_CONF_FRAMEBURST   __BIT(21)
 #define        AWIN_GMAC_MAC_CONF_MIISEL       __BIT(15)
 #define        AWIN_GMAC_MAC_CONF_FES100       __BIT(14)
+#define        AWIN_GMAC_MAC_CONF_DISABLERXOWN __BIT(13)
 #define        AWIN_GMAC_MAC_CONF_FULLDPLX     __BIT(11)
 #define        AWIN_GMAC_MAC_CONF_TXENABLE     __BIT(3)
 #define        AWIN_GMAC_MAC_CONF_RXENABLE     __BIT(2)
 
+#define        AWIN_GMAC_MAC_FFILT_PM          __BIT(4) /* promiscious multicast */
+#define        AWIN_GMAC_MAC_FFILT_HMC         __BIT(2) /* multicast hash compare */
+#define        AWIN_GMAC_MAC_FFILT_HUC         __BIT(1) /* unicast hash compare */
+#define        AWIN_GMAC_MAC_FFILT_PR          __BIT(0) /* promiscious mode */
+
 #define        AWIN_GMAC_MAC_INT_LPI           __BIT(10)
 #define        AWIN_GMAC_MAC_INT_TSI           __BIT(9)
 #define        AWIN_GMAC_MAC_INT_ANEG          __BIT(2)
@@ -69,7 +75,7 @@
 #define        AWIN_GMAC_DMA_CUR_RX_BUFADDR    0x1054
 #define        AWIN_GMAC_DMA_HWFEATURES        0x1058  /* not always implemented? */
 
-#define GMAC_MII_PHY_SHIFT             11
+#define        GMAC_MII_PHY_SHIFT              11
 #define        GMAC_MII_PHY_MASK               __BITS(15,11)
 #define        GMAC_MII_REG_SHIFT              6
 #define        GMAC_MII_REG_MASK               __BITS(10,6)
@@ -92,33 +98,42 @@
 #define        GMAC_MII_CLK_DIV18              0xf
 #define        GMAC_MII_CLKMASK                __BITS(5,2)
 
+#define        GMAC_BUSMODE_FIXEDBURST         __BIT(16)
+#define        GMAC_BUSMODE_PRIORXTX           __BITS(15,14)
+#define        GMAC_BUSMODE_PRIORXTX_41        3
+#define        GMAC_BUSMODE_PRIORXTX_31        2
+#define        GMAC_BUSMODE_PRIORXTX_21        1
+#define        GMAC_BUSMODE_PRIORXTX_11        0
+#define        GMCA_BUSMODE_PBL                __BITS(13,8) /* possible DMA
+                                                       burst len */
 #define        GMAC_BUSMODE_RESET              __BIT(0)
 
 #define        AWIN_GMAC_MII_IRQ               __BIT(0)
 
-#define        GMAC_DMA_OP_STOREFORWARD        __BIT(21)
-#define        GMAC_DMA_OP_FLUSHTX             __BIT(20)
-#define        GMAC_DMA_OP_TXSTART             __BIT(13)
-#define        GMAC_DMA_OP_TXSECONDFRAME       __BIT(2)
-#define        GMAC_DMA_OP_RXSTART             __BIT(1)
 
-#define GMAC_DMA_INT_NIE               __BIT(16) /* Normal/Summary */
-#define GMAC_DMA_INT_AIE               __BIT(15) /* Abnormal/Summary */
+#define        GMAC_DMA_OP_STOREFORWARD        __BIT(21) /* start TX with when a
+                                                   full frame is available */
+#define        GMAC_DMA_OP_FLUSHTX             __BIT(20) /* flush TX fifo */
+#define        GMAC_DMA_OP_TXSTART             __BIT(13) /* start TX DMA engine */
+#define        GMAC_DMA_OP_RXSTART             __BIT(1)  /* start RX DMA engine */
+
+#define        GMAC_DMA_INT_NIE                __BIT(16) /* Normal/Summary */
+#define        GMAC_DMA_INT_AIE                __BIT(15) /* Abnormal/Summary */
 #define        GMAC_DMA_INT_ERE                __BIT(14) /* Early receive */
 #define        GMAC_DMA_INT_FBE                __BIT(13) /* Fatal bus error */
 #define        GMAC_DMA_INT_ETE                __BIT(10) /* Early transmit */
-#define        GMAC_DMA_INT_RWE                __BIT(9) /* Receive watchdog */
-#define        GMAC_DMA_INT_RSE                __BIT(8) /* Receive stopped */
-#define        GMAC_DMA_INT_RUE                __BIT(7) /* Receive buffer unavailable */
-#define        GMAC_DMA_INT_RIE                __BIT(6) /* Receive interrupt */
-#define        GMAC_DMA_INT_UNE                __BIT(5) /* Tx underflow */
-#define        GMAC_DMA_INT_OVE                __BIT(4) /* Receive overflow */
-#define        GMAC_DMA_INT_TJE                __BIT(3) /* Transmit jabber */
-#define        GMAC_DMA_INT_TUE                __BIT(2) /* Transmit buffer unavailable */
-#define        GMAC_DMA_INT_TSE                __BIT(1) /* Transmit stopped */
-#define        GMAC_DMA_INT_TIE                __BIT(0) /* Transmit interrupt */
+#define        GMAC_DMA_INT_RWE                __BIT(9)  /* Receive watchdog */
+#define        GMAC_DMA_INT_RSE                __BIT(8)  /* Receive stopped */
+#define        GMAC_DMA_INT_RUE                __BIT(7)  /* Receive buffer unavail. */
+#define        GMAC_DMA_INT_RIE                __BIT(6)  /* Receive interrupt */
+#define        GMAC_DMA_INT_UNE                __BIT(5)  /* Tx underflow */
+#define        GMAC_DMA_INT_OVE                __BIT(4)  /* Receive overflow */
+#define        GMAC_DMA_INT_TJE                __BIT(3)  /* Transmit jabber */
+#define        GMAC_DMA_INT_TUE                __BIT(2)  /* Transmit buffer unavail. */
+#define        GMAC_DMA_INT_TSE                __BIT(1)  /* Transmit stopped */
+#define        GMAC_DMA_INT_TIE                __BIT(0)  /* Transmit interrupt */
 
-#define        GMAC_DMA_INT_MASK       __BITS(0,16)    /* all possible intr bits */
+#define        GMAC_DMA_INT_MASK       __BITS(0,16)      /* all possible intr bits */
 
 struct dwc_gmac_dev_dmadesc {
        uint32_t ddesc_status;
@@ -149,7 +164,7 @@
 
 /* for TX descriptors */
 #define        DDESC_CNTL_TXINT                __BIT(31)
-#define DDESC_CNTL_TXLAST              __BIT(30)
+#define        DDESC_CNTL_TXLAST               __BIT(30)
 #define        DDESC_CNTL_TXFIRST              __BIT(29)
 #define        DDESC_CNTL_TXCHECKINSCTRL       __BIT(27)
 #define        DDESC_CNTL_TXCRCDIS             __BIT(26)
@@ -157,7 +172,7 @@
 #define        DDESC_CNTL_TXCHAIN              __BIT(24)
 
 /* for RX descriptors */
-#define        DDESC_CNTL_RXINTDIS             __BIT(31)
+#define        DDESC_CNTL_RXINT                __BIT(31)
 #define        DDESC_CNTL_RXRINGEND            __BIT(25)
 #define        DDESC_CNTL_RXCHAIN              __BIT(24)