[src/trunk]: src/sys/arch/arm/include/arm32 Update a comment to reflect ARM A...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7bc11571c34d
branches:  trunk
changeset: 803463:7bc11571c34d
user:      skrll <skrll%NetBSD.org@localhost>
date:      Wed Oct 29 10:59:48 2014 +0000

description:
Update a comment to reflect ARM ARMv7

diffstat:

 sys/arch/arm/include/arm32/pte.h |  42 +++++++++++++++++++--------------------
 1 files changed, 20 insertions(+), 22 deletions(-)

diffs (63 lines):

diff -r 2caf2f84771b -r 7bc11571c34d sys/arch/arm/include/arm32/pte.h
--- a/sys/arch/arm/include/arm32/pte.h  Wed Oct 29 10:56:19 2014 +0000
+++ b/sys/arch/arm/include/arm32/pte.h  Wed Oct 29 10:59:48 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pte.h,v 1.18 2014/08/08 07:47:24 skrll Exp $   */
+/*     $NetBSD: pte.h,v 1.19 2014/10/29 10:59:48 skrll Exp $   */
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -304,34 +304,32 @@
 /*
  * Type Extension bits for ARM V6 and V7 MMU
  *
- * TEX C B                                    Shared
- * 000 0 0  Strong order                      yes
- * 000 0 1  Shared device                     yes
- * 000 1 0  write through, no write alloc     S-bit
- * 000 1 1  write back, no write alloc        S-bit
- * 001 0 0  non-cacheable                     S-bit
+ * TEX C B                                                    Shared
+ * 000 0 0  Strong order                                      yes
+ * 000 0 1  Shared device                                     yes
+ * 000 1 0  Outer and Inner write through, no write alloc     S-bit
+ * 000 1 1  Outer and Inner write back, no write alloc        S-bit
+ * 001 0 0  Outer and Inner non-cacheable                     S-bit
  * 001 0 1  reserved
  * 001 1 0  reserved
- * 001 1 1  write back, write alloc           S-bit
- * 010 0 0  Non-shared device                 no
+ * 001 1 1  Outer and Inner write back, write alloc           S-bit
+ * 010 0 0  Non-shared device                                 no
  * 010 0 1  reserved
  * 010 1 X  reserved
  * 011 X X  reserved
- * 1BB A A  BB for internal, AA for external  S-bit
+ * 1BB A A  BB for inner, AA for outer                        S-bit
  *
- *    BB    internal cache
- *    0 0   Non-cacheable non-buffered
- *    0 1   Write back, write alloc, buffered
- *    1 0   Write through, no write alloc, buffered
- *          (non-cacheable for MPCore)
- *    1 1   Write back, no write alloc, buffered
- *          (write back, write alloc for MPCore)
+ *    BB    inner cache
+ *    0 0   Non-cacheable
+ *    0 1   Write back, write alloc
+ *    1 0   Write through, no write alloc
+ *    1 1   Write back, no write alloc
  *
- *    AA    external cache
- *    0 0   Non-cacheable non-buffered
- *    0 1   Write back, write alloc, buffered
- *    1 0   Write through, no write alloc, buffered
- *    1 1   Write back, no write alloc, buffered
+ *    AA    outer cache
+ *    0 0   Non-cacheable
+ *    0 1   Write back, write alloc
+ *    1 0   Write through, no write alloc
+ *    1 1   Write back, no write alloc
  */
 
 #define        TEX_ARMV6_TEX   0x07            /* 3 bits in TEX */