[src/trunk]: src/sys/arch/arm/cortex Enable L2 prefetch on A9 if MP

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/633a63308251
branches:  trunk
changeset: 802478:633a63308251
user:      matt <matt%NetBSD.org@localhost>
date:      Tue Sep 16 22:00:22 2014 +0000

description:
Enable L2 prefetch on A9 if MP

diffstat:

 sys/arch/arm/cortex/a9_mpsubr.S |  8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diffs (22 lines):

diff -r 8ba52cf9c4a0 -r 633a63308251 sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S   Tue Sep 16 21:59:40 2014 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S   Tue Sep 16 22:00:22 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: a9_mpsubr.S,v 1.21 2014/09/15 19:02:38 skrll Exp $     */
+/*     $NetBSD: a9_mpsubr.S,v 1.22 2014/09/16 22:00:22 matt Exp $      */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -457,6 +457,12 @@
        //
        orr     r0, r0, #CORTEXA9_AUXCTL_FW     // enable cache/tlb/coherency
 #endif /* A5 || A9 */
+#if defined(CPU_CORTEXA9)
+       //
+       // Step 4b (continued on A9), ACTLR.L2PE=1)
+       //
+       orr     r0, r0, #CORTEXA9_AUXCTL_L2PE   // enable L2 cache prefetch
+#endif
 
        mcr     p15, 0, r0, c1, c0, 1           // ACTLR write
        isb