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[src/trunk]: src/sys/arch/x86 Several registers and bitfields named IOAPIC_* ...
details: https://anonhg.NetBSD.org/src/rev/bc5a793b024f
branches: trunk
changeset: 784357:bc5a793b024f
user: dyoung <dyoung%NetBSD.org@localhost>
date: Sat Jan 26 17:37:39 2013 +0000
description:
Several registers and bitfields named IOAPIC_* actually belong to the
LAPIC, so rename them LAPIC_* and move to a more appropriate header
file.
diffstat:
sys/arch/x86/include/i82093reg.h | 30 +-----------------------------
sys/arch/x86/include/i82489reg.h | 28 +++++++++++++++++++++++++++-
sys/arch/x86/pci/pci_intr_machdep.c | 22 ++++++++++++----------
3 files changed, 40 insertions(+), 40 deletions(-)
diffs (148 lines):
diff -r f573d7b9efc6 -r bc5a793b024f sys/arch/x86/include/i82093reg.h
--- a/sys/arch/x86/include/i82093reg.h Sat Jan 26 17:29:55 2013 +0000
+++ b/sys/arch/x86/include/i82093reg.h Sat Jan 26 17:37:39 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i82093reg.h,v 1.3 2011/08/17 14:55:11 dyoung Exp $ */
+/* $NetBSD: i82093reg.h,v 1.4 2013/01/26 17:37:39 dyoung Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -36,34 +36,6 @@
*/
#define IOAPIC_BASE_DEFAULT 0xfec00000
-#define IOAPIC_MSIADDR_BASE 0xfee00000
-#define IOAPIC_MSIADDR_DSTID_MASK __BITS(19, 12)
-#define IOAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4)
-#define IOAPIC_MSIADDR_RH __BIT(3)
-#define IOAPIC_MSIADDR_DM __BIT(2)
-#define IOAPIC_MSIADDR_RSVD1_MASK __BITS(1, 0)
-
-#define IOAPIC_MSIDATA_VECTOR_MASK __BITS(7, 0)
-#define IOAPIC_MSIDATA_DM_MASK __BITS(10, 8)
-#define IOAPIC_MSIDATA_DM_FIXED __SHIFTIN(0, IOAPIC_MSIDATA_DM_MASK)
-#define IOAPIC_MSIDATA_DM_LOPRI __SHIFTIN(1, IOAPIC_MSIDATA_DM_MASK)
-#define IOAPIC_MSIDATA_DM_SMI __SHIFTIN(2, IOAPIC_MSIDATA_DM_MASK)
-#define IOAPIC_MSIDATA_DM_RSVD0 __SHIFTIN(3, IOAPIC_MSIDATA_DM_MASK)
-#define IOAPIC_MSIDATA_DM_NMI __SHIFTIN(4, IOAPIC_MSIDATA_DM_MASK)
-#define IOAPIC_MSIDATA_DM_INIT __SHIFTIN(5, IOAPIC_MSIDATA_DM_MASK)
-#define IOAPIC_MSIDATA_DM_RSVD1 __SHIFTIN(6, IOAPIC_MSIDATA_DM_MASK)
-#define IOAPIC_MSIDATA_DM_EXTINT __SHIFTIN(7, IOAPIC_MSIDATA_DM_MASK)
-#define IOAPIC_MSIDATA_RSVD0_MASK __BITS(13, 11)
-#define IOAPIC_MSIDATA_LEVEL_MASK __BIT(14)
-#define IOAPIC_MSIDATA_LEVEL_DEASSERT __SHIFTIN(0, IOAPIC_MSIDATA_LEVEL_MASK)
-#define IOAPIC_MSIDATA_LEVEL_ASSERT __SHIFTIN(1, IOAPIC_MSIDATA_LEVEL_MASK)
-#define IOAPIC_MSIDATA_TRGMODE_MASK __BIT(15)
-#define IOAPIC_MSIDATA_TRGMODE_EDGE \
- __SHIFTIN(0, IOAPIC_MSIDATA_TRGMODE_MASK)
-#define IOAPIC_MSIDATA_TRGMODE_LEVEL \
- __SHIFTIN(1, IOAPIC_MSIDATA_TRGMODE_MASK)
-#define IOAPIC_MSIDATA_RSVD1_MASK __BITS(31, 16)
-
/*
* Memory-space registers.
*/
diff -r f573d7b9efc6 -r bc5a793b024f sys/arch/x86/include/i82489reg.h
--- a/sys/arch/x86/include/i82489reg.h Sat Jan 26 17:29:55 2013 +0000
+++ b/sys/arch/x86/include/i82489reg.h Sat Jan 26 17:37:39 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i82489reg.h,v 1.11 2012/01/20 18:47:04 hannken Exp $ */
+/* $NetBSD: i82489reg.h,v 1.12 2013/01/26 17:37:39 dyoung Exp $ */
/*-
* Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
@@ -139,6 +139,32 @@
# define LAPIC_DCRT_DIV64 0x09
# define LAPIC_DCRT_DIV128 0x0a
+#define LAPIC_MSIADDR_BASE 0xfee00000
+#define LAPIC_MSIADDR_DSTID_MASK __BITS(19, 12)
+#define LAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4)
+#define LAPIC_MSIADDR_RH __BIT(3)
+#define LAPIC_MSIADDR_DM __BIT(2)
+#define LAPIC_MSIADDR_RSVD1_MASK __BITS(1, 0)
+
+#define LAPIC_MSIDATA_VECTOR_MASK __BITS(7, 0)
+#define LAPIC_MSIDATA_DM_MASK __BITS(10, 8)
+#define LAPIC_MSIDATA_DM_FIXED __SHIFTIN(0, LAPIC_MSIDATA_DM_MASK)
+#define LAPIC_MSIDATA_DM_LOPRI __SHIFTIN(1, LAPIC_MSIDATA_DM_MASK)
+#define LAPIC_MSIDATA_DM_SMI __SHIFTIN(2, LAPIC_MSIDATA_DM_MASK)
+#define LAPIC_MSIDATA_DM_RSVD0 __SHIFTIN(3, LAPIC_MSIDATA_DM_MASK)
+#define LAPIC_MSIDATA_DM_NMI __SHIFTIN(4, LAPIC_MSIDATA_DM_MASK)
+#define LAPIC_MSIDATA_DM_INIT __SHIFTIN(5, LAPIC_MSIDATA_DM_MASK)
+#define LAPIC_MSIDATA_DM_RSVD1 __SHIFTIN(6, LAPIC_MSIDATA_DM_MASK)
+#define LAPIC_MSIDATA_DM_EXTINT __SHIFTIN(7, LAPIC_MSIDATA_DM_MASK)
+#define LAPIC_MSIDATA_RSVD0_MASK __BITS(13, 11)
+#define LAPIC_MSIDATA_LEVEL_MASK __BIT(14)
+#define LAPIC_MSIDATA_LEVEL_DEASSERT __SHIFTIN(0, LAPIC_MSIDATA_LEVEL_MASK)
+#define LAPIC_MSIDATA_LEVEL_ASSERT __SHIFTIN(1, LAPIC_MSIDATA_LEVEL_MASK)
+#define LAPIC_MSIDATA_TRGMODE_MASK __BIT(15)
+#define LAPIC_MSIDATA_TRGMODE_EDGE __SHIFTIN(0, LAPIC_MSIDATA_TRGMODE_MASK)
+#define LAPIC_MSIDATA_TRGMODE_LEVEL __SHIFTIN(1, LAPIC_MSIDATA_TRGMODE_MASK)
+#define LAPIC_MSIDATA_RSVD1_MASK __BITS(31, 16)
+
#define LAPIC_BASE 0xfee00000
#define LAPIC_IRQ_MASK(i) (1 << ((i) + 1))
diff -r f573d7b9efc6 -r bc5a793b024f sys/arch/x86/pci/pci_intr_machdep.c
--- a/sys/arch/x86/pci/pci_intr_machdep.c Sat Jan 26 17:29:55 2013 +0000
+++ b/sys/arch/x86/pci/pci_intr_machdep.c Sat Jan 26 17:37:39 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_intr_machdep.c,v 1.25 2012/06/15 14:07:44 yamt Exp $ */
+/* $NetBSD: pci_intr_machdep.c,v 1.26 2013/01/26 17:37:39 dyoung Exp $ */
/*-
* Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc.
@@ -73,7 +73,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.25 2012/06/15 14:07:44 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.26 2013/01/26 17:37:39 dyoung Exp $");
#include <sys/types.h>
#include <sys/param.h>
@@ -92,6 +92,8 @@
#include "opt_mpbios.h"
#include "opt_acpi.h"
+#include <machine/i82489reg.h>
+
#if NIOAPIC > 0 || NACPICA > 0
#include <machine/i82093reg.h>
#include <machine/i82093var.h>
@@ -391,8 +393,8 @@
is = ci->ci_isources[ih->ih_slot];
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL);
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_LO,
- IOAPIC_MSIADDR_BASE |
- __SHIFTIN(ci->ci_cpuid, IOAPIC_MSIADDR_DSTID_MASK));
+ LAPIC_MSIADDR_BASE |
+ __SHIFTIN(ci->ci_cpuid, LAPIC_MSIADDR_DSTID_MASK));
if (reg & PCI_MSI_CTL_64BIT_ADDR) {
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_HI,
0);
@@ -400,17 +402,17 @@
* EDGE
*/
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA64,
- __SHIFTIN(is->is_idtvec, IOAPIC_MSIDATA_VECTOR_MASK) |
- IOAPIC_MSIDATA_TRGMODE_EDGE | IOAPIC_MSIDATA_LEVEL_ASSERT |
- IOAPIC_MSIDATA_DM_FIXED);
+ __SHIFTIN(is->is_idtvec, LAPIC_MSIDATA_VECTOR_MASK) |
+ LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_LEVEL_ASSERT |
+ LAPIC_MSIDATA_DM_FIXED);
} else {
/* XXX according to the manual, ASSERT is unnecessary if
* EDGE
*/
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA,
- __SHIFTIN(is->is_idtvec, IOAPIC_MSIDATA_VECTOR_MASK) |
- IOAPIC_MSIDATA_TRGMODE_EDGE | IOAPIC_MSIDATA_LEVEL_ASSERT |
- IOAPIC_MSIDATA_DM_FIXED);
+ __SHIFTIN(is->is_idtvec, LAPIC_MSIDATA_VECTOR_MASK) |
+ LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_LEVEL_ASSERT |
+ LAPIC_MSIDATA_DM_FIXED);
}
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL,
PCI_MSI_CTL_MSI_ENABLE);
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