[src/trunk]: src/sys/arch/arm/samsung Explicitly mark MCUCTL_ISP_OFFSET as an...

[reinoud <reinoud%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/3a40f2a6209e
branches:  trunk
changeset: 796435:3a40f2a6209e
user:      reinoud <reinoud%NetBSD.org@localhost>
date:      Tue Jun 03 15:51:59 2014 +0000

description:
Explicitly mark MCUCTL_ISP_OFFSET as an unknown module to prevent confusion

diffstat:

 sys/arch/arm/samsung/exynos4_reg.h |  2 +-
 sys/arch/arm/samsung/exynos5_reg.h |  4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diffs (30 lines):

diff -r 50c8d7b4fca6 -r 3a40f2a6209e sys/arch/arm/samsung/exynos4_reg.h
--- a/sys/arch/arm/samsung/exynos4_reg.h        Tue Jun 03 15:06:36 2014 +0000
+++ b/sys/arch/arm/samsung/exynos4_reg.h        Tue Jun 03 15:51:59 2014 +0000
@@ -178,7 +178,7 @@
 #define EXYNOS4_MTCADC_ISP_OFFSET              0x02150000      /* (specialised?) AD Converter */
 #define EXYNOS4_PWM_ISP_OFFSET                 0x02160000      /* PWM */
 #define EXYNOS4_WDT_ISP_OFFSET                 0x02170000      /* Watch Dog Timer */
-#define EXYNOS4_MCUCTL_ISP_OFFSET              0x02180000      /* XXX micro controller control unit? */
+#define EXYNOS4_MCUCTL_ISP_OFFSET              0x02180000      /* power module control unit? */
 #define EXYNOS4_UART_ISP_OFFSET                        0x02190000      /* uart base clock */
 #define EXYNOS4_SPI0_ISP_OFFSET                        0x021A0000
 #define EXYNOS4_SPI1_ISP_OFFSET                        0x021B0000
diff -r 50c8d7b4fca6 -r 3a40f2a6209e sys/arch/arm/samsung/exynos5_reg.h
--- a/sys/arch/arm/samsung/exynos5_reg.h        Tue Jun 03 15:06:36 2014 +0000
+++ b/sys/arch/arm/samsung/exynos5_reg.h        Tue Jun 03 15:51:59 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: exynos5_reg.h,v 1.4 2014/05/21 13:02:46 reinoud Exp $  */
+/*     $NetBSD: exynos5_reg.h,v 1.5 2014/06/03 15:51:59 reinoud Exp $  */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -144,7 +144,7 @@
 #define EXYNOS5_USB2_DEVICE_LINK_OFFSET                0x02140000
 #define EXYNOS5_MIPI_HSI_OFFSET                        0x02160000
 #define EXYNOS5_SATA PHY CONTROL_OFFSET                0x02170000
-#define EXYNOS5_MCUCTL_IOP_OFFSET              0x02180000
+#define EXYNOS5_MCUCTL_IOP_OFFSET              0x02180000      /* XXX unknown XXX */
 #define EXYNOS5_WDT_IOP_OFFSET                 0x02190000
 #define EXYNOS5_PDMA0                          0x021A0000
 #define EXYNOS5_PDMA1                          0x021B0000