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[src/trunk]: src/sys separate buffer management codes 'mvxpbm.c' from if_mvxp...
details: https://anonhg.NetBSD.org/src/rev/5cf179bd3819
branches: trunk
changeset: 808797:5cf179bd3819
user: hsuenaga <hsuenaga%NetBSD.org@localhost>
date: Wed Jun 03 03:55:47 2015 +0000
description:
separate buffer management codes 'mvxpbm.c' from if_mvxpe.c.
the buffer management(ex. fill the rx descriptors/buffers) is done by H/W in
ARMADA XP/380, and is done by S/W in ARMADA 370. the H/W BM support is not yet
implemented, so all devices use the S/W management mode at this time.
diffstat:
sys/arch/arm/marvell/files.marvell | 5 +-
sys/arch/arm/marvell/mvsoc.c | 10 +-
sys/dev/marvell/files.armada | 8 +-
sys/dev/marvell/if_mvxpe.c | 569 ++++++++++--------------------------
sys/dev/marvell/if_mvxpereg.h | 16 +-
sys/dev/marvell/if_mvxpevar.h | 130 ++------
sys/dev/marvell/mvxpbm.c | 492 +++++++++++++++++++++++++++++++
sys/dev/marvell/mvxpbmvar.h | 139 +++++++++
8 files changed, 856 insertions(+), 513 deletions(-)
diffs (truncated from 1978 to 300 lines):
diff -r eb8c15d9362a -r 5cf179bd3819 sys/arch/arm/marvell/files.marvell
--- a/sys/arch/arm/marvell/files.marvell Wed Jun 03 03:34:38 2015 +0000
+++ b/sys/arch/arm/marvell/files.marvell Wed Jun 03 03:55:47 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.marvell,v 1.15 2015/06/03 03:34:38 hsuenaga Exp $
+# $NetBSD: files.marvell,v 1.16 2015/06/03 03:55:47 hsuenaga Exp $
#
# Configuration info for Marvell System on Chip support
#
@@ -58,6 +58,9 @@
# Gigabit Ethernet Controller Interface
attach mvgbec at mvsoc with mvgbec_mbus
+# ARMADA XP Buffer Manager
+attach mvxpbm at mvsoc with mvxpbm_mbus
+
# ARMADA XP Gigabit Ethernet Controller Interface
attach mvxpe at mvsoc with mvxpe_mbus
diff -r eb8c15d9362a -r 5cf179bd3819 sys/arch/arm/marvell/mvsoc.c
--- a/sys/arch/arm/marvell/mvsoc.c Wed Jun 03 03:34:38 2015 +0000
+++ b/sys/arch/arm/marvell/mvsoc.c Wed Jun 03 03:55:47 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.21 2015/06/03 03:04:21 hsuenaga Exp $ */
+/* $NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.21 2015/06/03 03:04:21 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $");
#include "opt_cputypes.h"
#include "opt_mvsoc.h"
@@ -685,6 +685,7 @@
{ ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
{ ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
#if NMVXPE > 0
+ { ARMADAXP(MV78130), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
#else
@@ -716,6 +717,7 @@
{ ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{ ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
#if NMVXPE > 0
+ { ARMADAXP(MV78160), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
{ ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
@@ -751,6 +753,7 @@
{ ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{ ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
#if NMVXPE > 0
+ { ARMADAXP(MV78230), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
{ ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
@@ -784,6 +787,7 @@
{ ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{ ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
#if NMVXPE > 0
+ { ARMADAXP(MV78260), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
{ ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
@@ -820,6 +824,7 @@
{ ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{ ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
#if NMVXPE > 0
+ { ARMADAXP(MV78460), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
{ ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
@@ -849,6 +854,7 @@
{ ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{ ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
#if NMVXPE > 0
+ { ARMADA370(MV6710), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
{ ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
#else
diff -r eb8c15d9362a -r 5cf179bd3819 sys/dev/marvell/files.armada
--- a/sys/dev/marvell/files.armada Wed Jun 03 03:34:38 2015 +0000
+++ b/sys/dev/marvell/files.armada Wed Jun 03 03:55:47 2015 +0000
@@ -1,7 +1,11 @@
-# $NetBSD: files.armada,v 1.1 2015/06/03 03:34:38 hsuenaga Exp $
+# $NetBSD: files.armada,v 1.2 2015/06/03 03:55:47 hsuenaga Exp $
# Configuration info for Marvell ARMADA integrated peripherals
+# ARMADA XP Buffer Manger
+device mvxpbm { [port = -1 ], [irq = -1] }
+file dev/marvell/mvxpbm.c
+
# ARMADA XP Gigabit Ethernet Controller Interface
define mvxpe { [port = -1 ], [irq = -1] }
-device mvxpe: ether, ifnet, arp, mii
+device mvxpe: mvxpbm, ether, ifnet, arp, mii
file dev/marvell/if_mvxpe.c mvxpe needs-flag
diff -r eb8c15d9362a -r 5cf179bd3819 sys/dev/marvell/if_mvxpe.c
--- a/sys/dev/marvell/if_mvxpe.c Wed Jun 03 03:34:38 2015 +0000
+++ b/sys/dev/marvell/if_mvxpe.c Wed Jun 03 03:55:47 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_mvxpe.c,v 1.1 2015/05/03 14:38:10 hsuenaga Exp $ */
+/* $NetBSD: if_mvxpe.c,v 1.2 2015/06/03 03:55:47 hsuenaga Exp $ */
/*
* Copyright (c) 2015 Internet Initiative Japan Inc.
* All rights reserved.
@@ -25,7 +25,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_mvxpe.c,v 1.1 2015/05/03 14:38:10 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_mvxpe.c,v 1.2 2015/06/03 03:55:47 hsuenaga Exp $");
#include "opt_multiprocessor.h"
@@ -58,6 +58,7 @@
#include <dev/marvell/marvellreg.h>
#include <dev/marvell/marvellvar.h>
+#include <dev/marvell/mvxpbmvar.h>
#include <dev/marvell/if_mvxpereg.h>
#include <dev/marvell/if_mvxpevar.h>
@@ -136,30 +137,20 @@
STATIC void mvxpe_linkdown(struct mvxpe_softc *);
STATIC void mvxpe_linkreset(struct mvxpe_softc *);
-/* Packet Buffer Manager(BM) */
-STATIC int mvxpe_bm_init(struct mvxpe_softc *);
-STATIC int mvxpe_bm_init_mbuf_hdr(struct mvxpe_bm_chunk *);
-STATIC struct mvxpe_bm_chunk *mvxpe_bm_alloc(struct mvxpe_softc *);
-STATIC void mvxpe_bm_free_mbuf(struct mbuf *, void *, size_t, void *);
-STATIC void mvxpe_bm_free_chunk(struct mvxpe_bm_chunk *);
-STATIC void mvxpe_bm_sync(struct mvxpe_bm_chunk *, size_t, int);
-STATIC void mvxpe_bm_lock(struct mvxpe_softc *);
-STATIC void mvxpe_bm_unlock(struct mvxpe_softc *);
-
/* Tx Subroutines */
STATIC int mvxpe_tx_queue_select(struct mvxpe_softc *, struct mbuf *);
STATIC int mvxpe_tx_queue(struct mvxpe_softc *, struct mbuf *, int);
STATIC void mvxpe_tx_set_csumflag(struct ifnet *,
struct mvxpe_tx_desc *, struct mbuf *);
-STATIC void mvxpe_tx_complete(struct mvxpe_softc *);
-STATIC void mvxpe_tx_queue_del(struct mvxpe_softc *, int);
+STATIC void mvxpe_tx_complete(struct mvxpe_softc *, uint32_t);
+STATIC void mvxpe_tx_queue_complete(struct mvxpe_softc *, int);
/* Rx Subroutines */
-STATIC void mvxpe_rx(struct mvxpe_softc *);
+STATIC void mvxpe_rx(struct mvxpe_softc *, uint32_t);
STATIC void mvxpe_rx_queue(struct mvxpe_softc *, int, int);
-STATIC int mvxpe_rx_queue_select(struct mvxpe_softc *, int *);
-STATIC void mvxpe_rx_reload(struct mvxpe_softc *);
-STATIC void mvxpe_rx_queue_reload(struct mvxpe_softc *, int);
+STATIC int mvxpe_rx_queue_select(struct mvxpe_softc *, uint32_t, int *);
+STATIC void mvxpe_rx_refill(struct mvxpe_softc *, uint32_t);
+STATIC void mvxpe_rx_queue_refill(struct mvxpe_softc *, int);
STATIC int mvxpe_rx_queue_add(struct mvxpe_softc *, int);
STATIC void mvxpe_rx_set_csumflag(struct ifnet *,
struct mvxpe_rx_desc *, struct mbuf *);
@@ -330,14 +321,19 @@
aprint_normal_dev(self, "Port Version %#x\n", sc->sc_version);
/*
- * Software based Buffer Manager(BM) subsystem.
- * Try to allocate special memory chunks for Rx packets.
- * Some version of SoC has hardware based BM(not supported yet)
+ * Buffer Manager(BM) subsystem.
*/
- if (mvxpe_bm_init(sc) != 0) {
- aprint_error_dev(self, "BM pool allocation failure\n");
+ sc->sc_bm = mvxpbm_device(mva);
+ if (sc->sc_bm == NULL) {
+ aprint_error_dev(self, "no Buffer Manager.\n");
goto fail;
}
+ aprint_normal_dev(self,
+ "Using Buffer Manager: %s\n", mvxpbm_xname(sc->sc_bm));
+ aprint_normal_dev(sc->sc_dev,
+ "%zu kbytes managed buffer, %zu bytes * %u entries allocated.\n",
+ mvxpbm_buf_size(sc->sc_bm) / 1024,
+ mvxpbm_chunk_size(sc->sc_bm), mvxpbm_chunk_count(sc->sc_bm));
/*
* make sure DMA engines are in reset state
@@ -526,9 +522,9 @@
STATIC int
mvxpe_evcnt_attach(struct mvxpe_softc *sc)
{
+#ifdef MVXPE_EVENT_COUNTERS
int q;
-#ifdef MVXPE_EVENT_COUNTERS
/* Master Interrupt Handler */
evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtxth, EVCNT_TYPE_INTR,
NULL, device_xname(sc->sc_dev), "RxTxTH Intr.");
@@ -1103,8 +1099,8 @@
rx->rx_queue_len = rx_default_queue_len[q];
if (rx->rx_queue_len > MVXPE_RX_RING_CNT)
rx->rx_queue_len = MVXPE_RX_RING_CNT;
- rx->rx_queue_th_received = rx->rx_queue_len / 4;
- rx->rx_queue_th_free = rx->rx_queue_len / 2;
+ rx->rx_queue_th_received = rx->rx_queue_len / MVXPE_RXTH_RATIO;
+ rx->rx_queue_th_free = rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO;
rx->rx_queue_th_time = (mvTclk / 1000) / 2; /* 0.5 [ms] */
/* Tx handle */
@@ -1113,8 +1109,9 @@
MVXPE_TX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_tx_desc) * i;
MVXPE_TX_MBUF(sc, q, i) = NULL;
/* Tx handle needs DMA map for busdma_load_mbuf() */
- if (bus_dmamap_create(sc->sc_dmat, sc->sc_bm.bm_chunk_size,
- MVXPE_TX_SEGLIMIT, sc->sc_bm.bm_chunk_size, 0,
+ if (bus_dmamap_create(sc->sc_dmat,
+ mvxpbm_chunk_size(sc->sc_bm),
+ MVXPE_TX_SEGLIMIT, mvxpbm_chunk_size(sc->sc_bm), 0,
BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW,
&MVXPE_TX_MAP(sc, q, i))) {
aprint_error_dev(sc->sc_dev,
@@ -1126,8 +1123,8 @@
tx->tx_queue_len = tx_default_queue_len[q];
if (tx->tx_queue_len > MVXPE_TX_RING_CNT)
tx->tx_queue_len = MVXPE_TX_RING_CNT;
- tx->tx_free_cnt = tx->tx_queue_len;
- tx->tx_queue_th_free = tx->tx_queue_len / 2;
+ tx->tx_used = 0;
+ tx->tx_queue_th_free = tx->tx_queue_len / MVXPE_TXTH_RATIO;
}
STATIC void
@@ -1144,7 +1141,7 @@
for (i = 0; i < MVXPE_RX_RING_CNT; i++) {
if (MVXPE_RX_PKTBUF(sc, q, i) == NULL)
continue;
- mvxpe_bm_free_chunk(MVXPE_RX_PKTBUF(sc, q, i));
+ mvxpbm_free_chunk(MVXPE_RX_PKTBUF(sc, q, i));
MVXPE_RX_PKTBUF(sc, q, i) = NULL;
}
rx->rx_dma = rx->rx_cpu = 0;
@@ -1158,7 +1155,7 @@
MVXPE_TX_MBUF(sc, q, i) = NULL;
}
tx->tx_dma = tx->tx_cpu = 0;
- tx->tx_free_cnt = tx->tx_queue_len;
+ tx->tx_used = 0;
}
STATIC void
@@ -1218,18 +1215,23 @@
MVXPE_WRITE(sc, MVXPE_PRXDQA(q), MVXPE_RX_RING_MEM_PA(sc, q));
/* Rx buffer size and descriptor ring size */
- reg = MVXPE_PRXDQS_BUFFERSIZE(sc->sc_bm.bm_chunk_size >> 3);
+ reg = MVXPE_PRXDQS_BUFFERSIZE(mvxpbm_chunk_size(sc->sc_bm) >> 3);
reg |= MVXPE_PRXDQS_DESCRIPTORSQUEUESIZE(MVXPE_RX_RING_CNT);
MVXPE_WRITE(sc, MVXPE_PRXDQS(q), reg);
DPRINTIFNET(ifp, 1, "PRXDQS(%d): %#x\n",
q, MVXPE_READ(sc, MVXPE_PRXDQS(q)));
/* Rx packet offset address */
- reg = MVXPE_PRXC_PACKETOFFSET(sc->sc_bm.bm_chunk_packet_offset >> 3);
+ reg = MVXPE_PRXC_PACKETOFFSET(mvxpbm_packet_offset(sc->sc_bm) >> 3);
MVXPE_WRITE(sc, MVXPE_PRXC(q), reg);
DPRINTIFNET(ifp, 1, "PRXC(%d): %#x\n",
q, MVXPE_READ(sc, MVXPE_PRXC(q)));
+ /* Rx DMA SNOOP */
+ reg = MVXPE_PRXSNP_SNOOPNOOFBYTES(MVXPE_MRU);
+ reg |= MVXPE_PRXSNP_L2DEPOSITNOOFBYTES(MVXPE_MRU);
+ MVXPE_WRITE(sc, MVXPE_PRXSNP(q), reg);
+
/* if DMA is not working, register is not updated */
KASSERT(MVXPE_READ(sc, MVXPE_PRXDQA(q)) == MVXPE_RX_RING_MEM_PA(sc, q));
return 0;
@@ -1412,58 +1414,51 @@
{
struct mvxpe_softc *sc = arg;
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
- uint32_t ic, datum = 0;
- int claimed = 0;
-
+ uint32_t ic, queues, datum = 0;
DPRINTSC(sc, 2, "got RXTX_TH_Intr\n");
MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtxth);
mvxpe_sc_lock(sc);
- for (;;) {
- ic = MVXPE_READ(sc, MVXPE_PRXTXTIC);
- if (ic == 0)
- break;
- MVXPE_WRITE(sc, MVXPE_PRXTXTIC, ~ic);
- datum = datum ^ ic;
- claimed = 1;
-
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