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[src/trunk]: src/sys/arch/mips/cavium Add wdog support
details: https://anonhg.NetBSD.org/src/rev/e66d62db0a39
branches: trunk
changeset: 808890:e66d62db0a39
user: matt <matt%NetBSD.org@localhost>
date: Sat Jun 06 20:52:16 2015 +0000
description:
Add wdog support
cleanup IPI and MP support
Add NMI support.
diffstat:
sys/arch/mips/cavium/octeon_cpunode.c | 261 +++++++++++++++++++++++++++++++--
sys/arch/mips/cavium/octeon_intr.c | 131 +++++++++++++++-
sys/arch/mips/cavium/octeonvar.h | 7 +-
3 files changed, 366 insertions(+), 33 deletions(-)
diffs (truncated from 651 to 300 lines):
diff -r eed07ea303c9 -r e66d62db0a39 sys/arch/mips/cavium/octeon_cpunode.c
--- a/sys/arch/mips/cavium/octeon_cpunode.c Sat Jun 06 20:15:35 2015 +0000
+++ b/sys/arch/mips/cavium/octeon_cpunode.c Sat Jun 06 20:52:16 2015 +0000
@@ -32,15 +32,24 @@
__KERNEL_RCSID(0, "$NetBSD");
#include "locators.h"
+#include "cpunode.h"
+#include "opt_multiprocessor.h"
+#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/device.h>
#include <sys/lwp.h>
#include <sys/cpu.h>
+#include <sys/wdog.h>
+
+#include <uvm/uvm.h>
+
+#include <dev/sysmon/sysmonvar.h>
#include <mips/cache.h>
#include <mips/cpuset.h>
#include <mips/mips_opcode.h>
+#include <mips/mips3_clock.h>
#include <mips/cavium/octeonvar.h>
#include <mips/cavium/dev/octeon_ciureg.h>
@@ -51,26 +60,35 @@
int cnaa_cpunum;
};
+struct cpunode_softc {
+ device_t sc_dev;
+ device_t sc_wdog_dev;
+ uint64_t sc_fuse;
+};
+
static int cpunode_mainbus_match(device_t, cfdata_t, void *);
static void cpunode_mainbus_attach(device_t, device_t, void *);
static int cpu_cpunode_match(device_t, cfdata_t, void *);
static void cpu_cpunode_attach(device_t, device_t, void *);
-CFATTACH_DECL_NEW(cpunode, 0,
+CFATTACH_DECL_NEW(cpunode, sizeof(struct cpunode_softc),
cpunode_mainbus_match, cpunode_mainbus_attach, NULL, NULL);
-CFATTACH_DECL_NEW(cpunode_cpu, 0,
+CFATTACH_DECL_NEW(cpu_cpunode, 0,
cpu_cpunode_match, cpu_cpunode_attach, NULL, NULL);
volatile __cpuset_t cpus_booted = 1;
+void octeon_reset_vector(void);
+
static int
cpunode_mainbus_print(void *aux, const char *pnp)
{
struct cpunode_attach_args * const cnaa = aux;
- aprint_normal(" core %d", cnaa->cnaa_cpunum);
+ if (cnaa->cnaa_cpunum != CPUNODECF_CORE_DEFAULT)
+ aprint_normal(" core %d", cnaa->cnaa_cpunum);
return UNCONF;
}
@@ -85,31 +103,44 @@
void
cpunode_mainbus_attach(device_t parent, device_t self, void *aux)
{
- uint64_t fuse = octeon_xkphys_read_8(CIU_FUSE);
+ struct cpunode_softc * const sc = device_private(self);
int cpunum = 0;
+ sc->sc_dev = self;
+ sc->sc_fuse = octeon_xkphys_read_8(CIU_FUSE);
+
aprint_naive(": %u core%s\n",
- popcount32((uint32_t)fuse),
- fuse == 1 ? "" : "s");
+ popcount32((uint32_t)sc->sc_fuse),
+ sc->sc_fuse == 1 ? "" : "s");
aprint_normal(": %u core%s",
- popcount32((uint32_t)fuse),
- fuse == 1 ? "" : "s");
+ popcount32((uint32_t)sc->sc_fuse),
+ sc->sc_fuse == 1 ? "" : "s");
const uint64_t cvmctl = mips_cp0_cvmctl_read();
aprint_normal(", %scrypto", (cvmctl & CP0_CVMCTL_NOCRYPTO) ? "no " : "");
aprint_normal((cvmctl & CP0_CVMCTL_KASUMI) ? "+kasumi" : "");
aprint_normal(", %s64bit-mul", (cvmctl & CP0_CVMCTL_NOMUL) ? "no " : "");
if (cvmctl & CP0_CVMCTL_REPUN)
aprint_normal(", unaligned-access ok");
+#ifdef MULTIPROCESSOR
+ aprint_normal(", booted %#" PRIx64, cpus_booted);
+#endif
aprint_normal("\n");
- for (; fuse != 0; fuse >>= 1, cpunum++) {
+ for (uint64_t fuse = sc->sc_fuse; fuse != 0; fuse >>= 1, cpunum++) {
struct cpunode_attach_args cnaa = {
.cnaa_name = "cpu",
.cnaa_cpunum = cpunum,
};
config_found(self, &cnaa, cpunode_mainbus_print);
}
+#if NWDOG > 0
+ struct cpunode_attach_args cnaa = {
+ .cnaa_name = "wdog",
+ .cnaa_cpunum = CPUNODECF_CORE_DEFAULT,
+ };
+ config_found(self, &cnaa, cpunode_mainbus_print);
+#endif
}
int
@@ -118,8 +149,8 @@
struct cpunode_attach_args * const cnaa = aux;
const int cpunum = cf->cf_loc[CPUNODECF_CORE];
- return cpunum == CPUNODECF_CORE_DEFAULT
- || cpunum == cnaa->cnaa_cpunum;
+ return strcmp(cnaa->cnaa_name, cf->cf_name) == 0
+ && (cpunum == CPUNODECF_CORE_DEFAULT || cpunum == cnaa->cnaa_cpunum);
}
#if defined(MULTIPROCESSOR)
@@ -129,8 +160,9 @@
{
struct cpu_info * const ci = arg;
+ atomic_or_64(&curcpu()->ci_flags, CPUF_PRESENT);
+
KASSERT(MIPS_KSEG0_P(load_addr));
- KASSERT(!MIPS_CACHE_VIRTUAL_ALIAS);
#ifdef MULTIPROCESSOR
KASSERT(!CPU_IS_PRIMARY(curcpu()));
#endif
@@ -178,34 +210,68 @@
ok = mips_fixup_exceptions(octeon_fixup_cpu_info_references, ci);
KASSERT(ok);
- (void) splhigh();
+ (void) splhigh(); // make sure interrupts are masked
-#ifdef DEBUG
KASSERT((mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM) == ci->ci_cpuid);
KASSERT(curcpu() == ci);
-#endif
+ KASSERT(ci->ci_cpl == IPL_HIGH);
+ KASSERT((mips_cp0_status_read() & MIPS_INT_MASK) == 0);
}
static void
octeon_cpu_run(struct cpu_info *ci)
{
+ octeon_intr_init(ci);
+
+ mips3_initclocks();
+ KASSERTMSG(ci->ci_cpl == IPL_NONE, "cpl %d", ci->ci_cpl);
+ KASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
+
+ aprint_normal("%s: ", device_xname(ci->ci_dev));
+ cpu_identify(ci->ci_dev);
}
#endif /* MULTIPROCESSOR */
static void
cpu_cpunode_attach_common(device_t self, struct cpu_info *ci)
{
+ struct cpu_softc * const cpu __diagused = ci->ci_softc;
+
ci->ci_dev = self;
self->dv_private = ci;
+ KASSERTMSG(cpu != NULL, "ci %p index %d", ci, cpu_index(ci));
+
+#if NWDOG > 0 || defined(DDB)
+ void **nmi_vector = (void *)MIPS_PHYS_TO_KSEG0(0x800 + 32*ci->ci_cpuid);
+ *nmi_vector = octeon_reset_vector;
+
+ struct vm_page * const pg = mips_pmap_alloc_poolpage(UVM_PGA_ZERO);
+ KASSERT(pg != NULL);
+ const vaddr_t kva = mips_pmap_map_poolpage(VM_PAGE_TO_PHYS(pg));
+ KASSERT(kva != 0);
+ ci->ci_xnext = (void *)(kva + PAGE_SIZE - sizeof(struct kernframe));
+#endif
+
+#ifdef WDOG
+ cpu->cpu_wdog_sih = softint_establish(SOFTINT_CLOCK|SOFTINT_MPSAFE,
+ wdog_cpunode_poke, cpu);
+ KASSERT(cpu->cpu_wdog_sih != NULL);
+#endif
+
aprint_normal(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n",
ci->ci_cpu_freq / 1000000,
(ci->ci_cpu_freq % 1000000) / 10000,
ci->ci_cycles_per_hz, ci->ci_divisor_delay);
- aprint_normal("%s: ", device_xname(self));
- cpu_identify(self);
+ if (CPU_IS_PRIMARY(ci)) {
+ aprint_normal("%s: ", device_xname(self));
+ cpu_identify(self);
+ }
cpu_attach_common(self, ci);
+#ifdef MULTIPROCESSOR
+ KASSERT(cpuid_infos[ci->ci_cpuid] == ci);
+#endif
}
void
@@ -235,8 +301,169 @@
ci->ci_softc->cpu_ci = ci;
cpu_cpunode_attach_common(self, ci);
+
+ KASSERT(ci->ci_data.cpu_idlelwp != NULL);
+ for (int i = 0; i < 100 && !CPUSET_HAS_P(cpus_hatched, cpunum); i++) {
+ delay(10000);
+ }
+ if (!CPUSET_HAS_P(cpus_hatched, cpunum)) {
+#ifdef DDB
+ aprint_verbose_dev(self, "hatch failed ci=%p flags=%#"PRIx64"\n", ci, ci->ci_flags);
+ cpu_Debugger();
+#endif
+ panic("%s failed to hatch: ci=%p flags=%#"PRIx64,
+ cpu_name(ci), ci, ci->ci_flags);
+ }
#else
aprint_naive(": disabled\n");
aprint_normal(": disabled (uniprocessor kernel)\n");
#endif
}
+
+#if NWDOG > 0
+struct wdog_softc {
+ struct sysmon_wdog sc_smw;
+ device_t sc_dev;
+ u_int sc_wdog_period;
+ bool sc_wdog_armed;
+};
+
+#ifndef OCTEON_WDOG_PERIOD_DEFAULT
+#define OCTEON_WDOG_PERIOD_DEFAULT 4
+#endif
+
+static int wdog_cpunode_match(device_t, cfdata_t, void *);
+static void wdog_cpunode_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(wdog_cpunode, sizeof(struct wdog_softc),
+ wdog_cpunode_match, wdog_cpunode_attach, NULL, NULL);
+
+static int
+wdog_cpunode_setmode(struct sysmon_wdog *smw)
+{
+ struct wdog_softc * const sc = smw->smw_cookie;
+
+ if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
+ if (sc->sc_wdog_armed) {
+ CPU_INFO_ITERATOR cii;
+ struct cpu_info *ci;
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ struct cpu_softc * const cpu = ci->ci_softc;
+ uint64_t wdog = mips64_ld_a64(cpu->cpu_wdog);
+ wdog &= ~CIU_WDOGX_MODE;
+ mips64_sd_a64(cpu->cpu_pp_poke, wdog);
+ aprint_verbose_dev(sc->sc_dev,
+ "%s: disable wdog=%#"PRIx64"\n",
+ cpu_name(ci), wdog);
+ mips64_sd_a64(cpu->cpu_wdog, wdog);
+ mips64_sd_a64(cpu->cpu_pp_poke, wdog);
+ }
+ sc->sc_wdog_armed = false;
+ }
+ } else if (!sc->sc_wdog_armed) {
+ kpreempt_disable();
+ struct cpu_info *ci = curcpu();
+ if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
+ smw->smw_period = OCTEON_WDOG_PERIOD_DEFAULT;
+ }
+ uint64_t wdog_len = smw->smw_period * ci->ci_cpu_freq;
+ //
+ // This wdog is a 24-bit counter that decrements every 256
+ // cycles. This is then a 32-bit counter so as long wdog_len
+ // doesn't overflow a 32-bit value, we are fine. We write the
+ // 16-bits of the 32-bit period.
+ if ((wdog_len >> 32) != 0) {
+ return EINVAL;
+ }
+ sc->sc_wdog_period = smw->smw_period;
+ CPU_INFO_ITERATOR cii;
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ struct cpu_softc * const cpu = ci->ci_softc;
+ uint64_t wdog = mips64_ld_a64(cpu->cpu_wdog);
+ wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN);
+ wdog |= __SHIFTIN(3, CIU_WDOGX_MODE);
+ wdog |= __SHIFTIN(wdog_len >> 16, CIU_WDOGX_LEN);
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