[src/trunk]: src/sys/arch/arm/omap Disable flow control with CPSW_SS FLOW_CON...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9d8a0197735b
branches:  trunk
changeset: 807628:9d8a0197735b
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Thu Apr 16 21:50:35 2015 +0000

description:
Disable flow control with CPSW_SS FLOW_CONTROL register (cherry-picked
from FreeBSD driver). Resolves device timeout / watchdog issues for me.

diffstat:

 sys/arch/arm/omap/if_cpsw.c    |  7 +++++--
 sys/arch/arm/omap/if_cpswreg.h |  1 +
 2 files changed, 6 insertions(+), 2 deletions(-)

diffs (39 lines):

diff -r d4d8f6dbdba0 -r 9d8a0197735b sys/arch/arm/omap/if_cpsw.c
--- a/sys/arch/arm/omap/if_cpsw.c       Thu Apr 16 19:53:19 2015 +0000
+++ b/sys/arch/arm/omap/if_cpsw.c       Thu Apr 16 21:50:35 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_cpsw.c,v 1.11 2015/03/26 22:00:45 skrll Exp $       */
+/*     $NetBSD: if_cpsw.c,v 1.12 2015/04/16 21:50:35 jmcneill Exp $    */
 
 /*
  * Copyright (c) 2013 Jonathan A. Kollasch
@@ -53,7 +53,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.11 2015/03/26 22:00:45 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.12 2015/04/16 21:50:35 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -954,6 +954,9 @@
        }
        sc->sc_rxhead = 0;
 
+       /* turn off flow control */
+       cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
+
        /* align layer 3 header to 32-bit */
        cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN);
 
diff -r d4d8f6dbdba0 -r 9d8a0197735b sys/arch/arm/omap/if_cpswreg.h
--- a/sys/arch/arm/omap/if_cpswreg.h    Thu Apr 16 19:53:19 2015 +0000
+++ b/sys/arch/arm/omap/if_cpswreg.h    Thu Apr 16 21:50:35 2015 +0000
@@ -37,6 +37,7 @@
 #define CPSW_SS_SOFT_RESET             (CPSW_SS_OFFSET + 0x08)
 #define CPSW_SS_STAT_PORT_EN           (CPSW_SS_OFFSET + 0x0C)
 #define CPSW_SS_PTYPE                  (CPSW_SS_OFFSET + 0x10)
+#define CPSW_SS_FLOW_CONTROL           (CPSW_SS_OFFSET + 0x24)
 #define CPSW_SS_RGMII_CTL              (CPSW_SS_OFFSET + 0x88)
 
 #define CPSW_PORT_OFFSET               0x0100